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Click here or scroll down to respond to this candidateCandidate's Name
Raleigh, NC EMAIL AVAILABLE +1 Street Address 9324 032 https://LINKEDIN LINK AVAILABLEOBJECTIVEDesign Engineer with hands-on experience in ASIC design, verification, and system-level validation. Successfully implementedand maintained test scripts at Harman International, and designed PCBs at Skanray Technologies. Proficient in using tools likeTestRunner, Allegro PCB Design, and Diagnostic Engineering Tool (DET).EDUCATIONNORTH CAROLINA STATE UNIVERSITY Aug 2022 - May 2024Master of Science in Computer Engineering 3.4/4.0 CGPARelevant Coursework: ASIC and FPGA Design with Verilog, ASIC Verification, VLSI Systems Design, MicroprocessorArchitecture, Architecture of Parallel Computers, Advanced Verification with Universal Verification Methodology (UVM)THE OXFORD COLLEGE OF ENGINEERING Aug 2018 - Aug 2022Bachelor of Engineering (Electronics and Communication Engineering) 8.78/10 CGPATECHNICAL SKILLSProgramming Languages : C, C++, Verilog, SystemVerilog, Python, VHDLWorking Platforms : PSpice, HSpice, MATLAB, Xilinx, Allegro Design, UVMDesign Tools : Cadence Virtuoso, Cadence/Calibre DRC, LVS tools, Questa Sim, Synopsys VirtuosoOperating Systems : Ubuntu, Windows XP, 7 and abovePROFESSIONAL EXPERIENCEHARMAN INTERNATIONAL, Novi, Michigan System Test, Summer Intern May 2023 - Aug 2023Implemented and maintained test scripts using TestRunner Software to automate testing procedures, ensuringcomprehensive coverage across all programs.Set up and validated validation vehicles for FORD Audio systems utilizing Diagnostic Engineering Tool (DET),demonstrating proficiency in system debugging and validation.SKANRAY TECHNOLOGIES, Mysuru (India) Intern Mar 2021 - April 2021Gained hands-on experience of designing PCB for the systems using Allegro PCB Design software.Acquired knowledge of industry-level medical equipment manufacturing processes, demonstrating a practicalunderstanding of hardware design principles.PROJECT EXPERIENCEFUNCTIONAL VERIFICATION OF LC-3Developing a Testbench and environment for the verification of LC-3 microcontroller. Developing components likeagent, monitor, driver, generator and verified it with a predictor golden reference model and scoreboard.FUNCTIONAL VERIFICATION OF I2CMB CONTROLLERCreated an I2C BFM, layered testbench containing different components such as an agent, monitor, driver, sequencer etc.,and a test plan for the functional verification of I2C multi-master bus controller.Ran verification test cases on System Verilog testbenches to achieve near 100% coverage.Performed simulations and debugging on Mentor Graphics Questa Sim.ASIC DESIGN OF MULTI-STAGE DEEP NEURAL NETWORKSWorked on building a Deep neural network containing convolution layer which takes the input and kernel matrix andcomputes the input to a Relu function to saturate negative values to 0, which then passes through the max pooling layer.Conducted design validation through Modelsim simulations to ensure functionality. Used Synopsys's DesignWare forsynthesis, optimizing performance to achieve maximum efficiency per area.64 BIT (16x4) DUAL PORT SRAMDesigned SRAM cell using 8T non precharge type cell for reducing the Energy-Area-Delay product, which is our performancemetric.Verified clean LVS and DRC checks on Synopsys Virtuoso, and simulated on Questasim.IMPLEMENTATION OF FLEXIBLE CACHE AND MEMORY HIERARCHY SIMULATORDesigned a simulator which implements write-back, write allocation and LRU replacement policy to compare the miss rate,AAT, performance, area and energy of different memory hierarchy configurations.Developed a cache module that can be used at any level in a memory hierarchy which supports any cache size, associativityand block size. |
