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Click here or scroll down to respond to this candidateSummary of QualificationsI am a skilled electrical engineer with 17 years of industry experience. I am always seeking to learn new things. I keep an open mind to new methodologies and solutions, while maintaining a philosophy of bringing problems back to first principles. I collaborate well with a team and hold myself accountable for my work.Skills:PCB design experienceProficient with design cycle management from product specification to manufacturing release.Power conversion and distribution architecture, power budget/efficiency analysis, load provisioning and regulation, IR loss, power integrity.Analog design, power conversion, filter design, loop compensation, signal conditioning, RF front end design.Modeling and simulation of DC-DC and AC-DC converters, RF, control systems. Time domain, frequency domain, spectral analysis.Behavioral, Finite Element and S-parameter modeling techniques with Spice, HFSS, AWR, MATLAB/Simulink and various other simulators.Practical understanding of electromagnetic principles for EMI/EMC, impedance controlSignal integrity experience implementing high-speed serial interfaces (10G/40G ethernet, 56G/112G PAM4 raw NRZ, PCIe, MIPI, SDI, USB).Well versed in component selection and sourcing.Experience debugging interfaces at various levels of the protocol stack (including GBe, PCIe, SATA, I2C, CAN, SPI, SDI, MIPI, USB, UART).Familiar with laboratory test and measurement equipment (O-scopes, function generators, logic/vector/spectrum analyzers).RTL design/verification experienceExpertise in Verilog, VHDL and SystemVerilog RTL design.Micro-architecture, implementation and testing of custom IP blocksThird party IP integration and verification (UPF, IP-Xact register and document generation, acceptance testing).Verification using self-checking testbenches, constrained randomization and coverage metrics.Behavioral modeling of subsystems for functional and performance analysis (C++, Matlab/Simulink, Python).Static timing analysis, techniques for resolving setup and hold violations, mitigation for clock uncertainty.Script development for design reuse, configuration, build automation, and testing with Python, TCL, BASH, C shell.Continuous integration environments with nightly regression builds.Experience with designs utilizing:SOCs, real time controllers, FPGAs (with and without embedded ARM or soft processor), DSP processors.Bus fabric: Memory mapped, streaming, and control/status busses (AXI-M/S/lite, AHB, NoC).Memory systems (HBM, DRAM, Cache, SRAM).Direct Memory Access engines (linear addressing, scatter gather, fly-by mode).Multiple asynchronous clock and reset domains, isolated power islands.DSP subsystems: MACs, Image, video, audio, and encryption DSP subsystems, digital filter design.Caches, ROMs, SRAM, EEPROM.Peripheral communication interfaces (IIC, SPI, CAN, Serial, USB, PCIe)Non-custom blocks (Bandgap references, PLLs, Power gates, clock dividers).Field Applications experienceDeveloping comprehensive knowledge of product line offerings, emerging applications, competitive position, roadmaps, and release schedules.Understanding each customers market opportunities and challenges and finding ways to add value.Tracking of existing and future customer programs, key stakeholders and timelines.Engaging and understanding customer architecture and design team challenges.Creation and presentation of technical and marketing materials for customer training and value propositions.Tailoring presentations to highlight key information relevant to the roles of the specific audience (Eg. Management vs. Engineering).Performing detailed design reviews and collaborating with design teams.Aggregating feedback from customers and serving as internal customer advocate.Project management experiencePreparation and presentation of technology demos, executive summaries, status reports, timely escalations, and vendor negotiations.Familiarity with Agile methodology.System block and flow diagrams, milestone schedules, scrum.Technical documentation generation for internal/external customers.EDA toolsDesign Compiler, Synplify, Vivado, Quartus, Lint/CDC/RDC/DFT, ModelSim, Questa, Synopsys VCS, NCSim, Altium, Allegro, ORCAD, XpeditionBuild, revision control and change management toolsGit, SVN, TKDiff, Chron, Jenkins, MakeProductivity toolsMS office, PowerPoint, Visio, Project, Jira, component databases, Vim, Emacs, Visual Studio, Diff toolsWork ExperienceField Application EngineerReal Intent, Sunnyvale, CA (March 2022 Sept. 2023 )Fostered business relationships with customer accounts. Provided pre- and post-sales support by developing and presenting technical marketingand training material, assisted with application challenges and promoted solutions with Real Intent static sign-off tools.Technical support for customer product evaluation pilot programs performing integration of Ascent Lint, Ascent Auto-Formal, Meridian CDC, Meridian RDC, and other static signoff tools.Employed custom build and bootstrap scripts coupled with advanced tool suite knowledge to achieve tailored/custom tool integrations (BASH, MAKE, SHELL, TCL, Perl).Developed Verilog RTL and VHDL RTL projects to serve as customer templates, demonstrate tool functionality and resolve customer issues.Hosted customer technical training sessions.Performed extensive QA to enable critical tool release milestones.Field Application EngineerXilinx, San Jose, CA (Dec 2017 Feb 2022)Consulted strategic clients on custom architectures, program requirements and implementation details for FPGA focused projects,including custom RTL design from scratch, verification, integration, and documentation. Promoted solutions with Xilinx silicon and tools, achievingseveral design-wins to secure millions in revenue.Forged relationships with design teams and served as the primary resource for technical questions relating to Xilinx products.Prepared and presented customer technical training sessions.Created Verilog, System Verilog and VHDL RTL designs for customer demos and special requests.Developed application examples utilizing AXI infrastructure, Serial IO, Linux device tree integration.Provided architectural, RTL design, and IP integration guidance.Reviewed system block diagrams, schematics, PCB layouts and RTL implementation.Performed Static Timing Analysis and assisted customers to resolve issues with timing closure.Debugged functional simulation results with Synopsys VCS and Modelsim.Prepared detailed reports outlining design improvement recommendations.Assisted with board bring up on customer premises. Set up experiments for failure analysis using lab equipment. Employed code changes, board rework and system work arounds where appropriate.ASIC Design EngineerHP Inc. Vancouver, WA (December 2014 May 2017)Designed, integrated, and verified new and existing RTL/IP on next generation SOC projects (ARM based)Configured AXI memory mapped and streaming interfaces for optimal traffic throughput and lockup safe operationDesign/redesign of sliding aperture filters (FIR filters, min/max/median filter, pixel interpolation).Evaluation of legacy code for reuse or deprecation.Functional simulation and verification using Synopsys VCSIntegration of designs into UVM testbench for constrained random verification.Drove designs through front end signoff (coverage, STA, DRC, Lint, CDC, LEC, functional and code coverage score).Coordinated vendor pilot program for experimental high bandwidth chip to chip interface IP.Integrated and maintained peripheral communication IP (UART, SPI, I2C, GPIO).Performed board design reviews and assisted with bring-up for product teams.Hardware/FPGA Design EngineerGrass Valley, Hillsboro, OR (November 2012- December 2014)Hardware design lead for video production and routing equipment projects.Member of the steering team for a product line overhaul to reduce costs by using IP networking infrastructure.Developed, integrated, and debugged multiple Verilog RTL designs for projects targeting current generation FPGAs.Performed Static Timing analysis and mitigated timing closure issues.Implemented AXI-S and AXI-M interfaces for IP subsystems on Xilinx FPGAs.Delivered designs for complex ARM /FPGA /DSP based circuit boards on schedule with a consistently low error rate.Utilized Virtex/Kintex class FPGAs, ARM SoC, TI DSP, 3Gb/s serial IO, 12G optical IO.Investigated/implemented digital PLL solution for phase locking asynchronous video streams.Re-factored and improved SDI digital video IO IP (Transceiver control/data interfaces, NRZI, decoder, barrel shifter, error checker).Developed scripts for build automation and various EDA tasks.Work Experience continuedApplication EngineerTransim Technologies, Portland, OR (April 2009 November 2012)Managed customer accounts and projects with multi-disciplinary teams to deliver customized software-as-a-service solutions.Developed complex analog and digital simulation models using Pspice, Simplis, Microwave Office, HFSS, MATLAB, and other simulation enginesDelivered AC/DC DC/DC converter IC simulation models (buck, boost, flyback, inverting boost) using voltage, current and hysteretic (sliding mode) feedback control.Created signal conditioner, Mixer, ADC and PLL simulation models.Performed time domain, frequency domain, spectral and network simulations using Linear/Non-linear/cycle averaged-linearized modelsDesigned and scripted algorithms for control loop compensation and filter designDeveloped scripts for Microcode/opcode generationPrototyped multiple marketing projects which ultimately led to new contracts and increased revenue.Created and administered comprehensive multi-day training course for customers and new engineers to accelerate content creation for Transim hosted customer tools.Trained teams around the world using the curriculum I developed, covering DC-DC converter basics, simulation optimization, control theory and software compatibility.Hardware Design EngineerOmneon Video Networks, Beaverton, OR (April 2007 April 2009)Hardware design lead for video server products used in broadcast media applications.Executed Design, verification and bring up of new products.Wrote specifications outlining detailed microarchitecture, functionality, and scope of hardware systems.Captured schematics, selected components, created layout constraints and guided layout designers.Hosted schematic and layout reviews.Performed signal integrity simulation and analysis with SPICE and finite element solvers.Managed bill of materials, manufacturing handoff, ECOs, First article inspections, board and system bring up, prototype spins, and production release.Designed Verilog RTL code for FPGA/ CPLDs including self-checking test benches for integration into a continuous integration environment.Performed compliance testing and mitigation for EMI/EMC, return loss, crosstalk, inter-symbol interference issues.Sustained, debugged and redesigned existing legacy products with field issues.EducationB.S. Electrical EngineeringPortland State University, Portland, ORGPA: 3.77Activities and HonorsGraduated with honors.Eta Kappa Nu, Electrical and Computer Engineering honor society, Vice President, Portland State University (2006-2007).Deans list six consecutive quarters.Completed a 6-month internship at Tektronix designing analog circuitry and implementing a digital CPLD design used in desk top oscilloscopes.Worked as an undergraduate research assistant in the Northwest Electromagnetics and Acoustics Research Lab doing Physics simulation and DSP research funded by the Office of Naval Research. I modeled 2DxN acoustic waves propagating through a realistic ocean impedance and bathymetry environment using modal analysis. This included a simulation of a real-life 2D phased array. deployed off of the coast of Florida, to characterize active beamforming performance using the covariance matrix. The simulations were performed in Matlab and presented for academic credit.Research lab assistant for Solid State physics lab. I developed control and data acquisition programs using LabView and C. I Assisted graduate students by setting up and configuring control and measurement equipment for Solar Cell and LED characteristics testing. I designed and implemented automated stimulus control and measurement fixtures for Zinc oxide nano-tube growth processes.References:Reid McClain Intel Senior FPGA engineerPHONE NUMBER AVAILABLE EMAIL AVAILABLERobbie Ward EETech CTOPHONE NUMBER AVAILABLE EMAIL AVAILABLEPeter Kim AMD Technical Sales EngineerPHONE NUMBER AVAILABLE EMAIL AVAILABLECorey Fleischer Real Intent Director of Sales SW US regionPHONE NUMBER AVAILABLE EMAIL AVAILABLE |
