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Click here or scroll down to respond to this candidate1Candidate's Name
ASIC/FPGA Design Engineer/Research ScientistEMAIL AVAILABLE LINKEDIN LINK AVAILABLE Cell: PHONE NUMBER AVAILABLE TECHNICAL SKILLS ASIC/FPGA Electrical Engineer skilled in digital and analog circuit design. Specialize in Verilog and VHDL high speed digital logic design for ASICS/FPGAs. Integration and design of FPGA for High performance computing (HPC) development. Pioneered ASIC chip and board design for IBM multiprocessing shared memory synchronization. Designed and developed a special purpose floating point unit for digital signal processing. Expert in timing circuitry, clock tree design, and clock synchronization. Extensive experience in RTL simulations, synthesis, and verification. Analog/RF/mixed-signal design and development with interface to FPGA and communication protocols. Held technical leadership positions in Northrop Grumman, Lockheed Martin, and IBM. ADDITIONAL TECHNICAL SKILLS Artificial Intelligence and Algorithm Development. Quantum computing RSFQ Analog Circuit Design. Invented the usage of Optical Interconnects for VLSI chip design using Vertical Cavity Surface Emitting Lasers. Established Architecture and logic design for inter-chip and IBM Inter Processor Communication. Developed a novel method for the usage of Nanotechnology for sensor applications. Magneto-resistive RAM (NRAM) nanotechnology memory usage for radar applications. EDUCATION PHD: Research and coursework toward PHD in Electrical Engineering, Columbia University New York, NY. MS: Electrical Engineering Major VLSI Chip Design, Columbia University, New York, NY. Coursework: Digital Logic, Analog IC Design, Microelectronics, Optoelectronics, Infrared Lasers, Imaging and Sensing, Parallel Processor Systolic Array Design. BS: Mathematics and Chemistry, Memphis State University, Memphis, TN. Graduate Summer Program: Stanford University, Stanford, CA, Electrical and Aerospace Engineering. WORK EXPERIENCENorthrop Grumman (Northridge, CA) Senior Principal Programmable Logic Engineer (June 2021 Sept 2023) Senior Principal Design Engineer Digital FPGA Design and Development Trouble shooting Intel FPGA design for the FPGA group. Worked with IT group to solve computer and tool problems for the department members. Tools: Xilinx, Quartus, Questa, Microsemi, Languages VHDL and Verilog. DAVID J. YVARS GROUP (RAYMOND JAMES - VALHALLA, NY) (2018 2019) Senior Software Engineer Artificial Intelligence and Algorithm Development Developed bots (Programmed Robots) to automate repetitive tasks for in depth financial analysis. Artificial Intelligence Tools: Intellibot graphics, python, C++. 2Lockheed Martin Missiles and Space Sunnyvale, CA (2017 - 2018) Senior FPGA Design Engineer Modified and documented existing satellite communications hardware. Responsibilities include RTL coding, placement-driven synthesis, logic debugging, timing closure and documentation standards. Performed analysis and proposed modifications to online chips to mitigate and tolerate radiation damage. Investigated Single Event Upsets as well as structural modifications to hardware on Xilinx chips to enhance radiation hardening. Author of company coding standards for FPGAs for Lockheed Martin Space Systems. Tools: Xilinx, Quartus, Microsemi, Implementation Languages Verilog/System Verilog/VHDL IBM RESEARCH CONTRACTOR GONZER AND ASSOCIATES AT YORKTOWN HEIGHTS, NY (2015 2017) Analog/Digital Circuit Design Engineer Quantum Computing Research into the use of RSFQ (Rapid Single Flux Quantum) circuits using Josephson junctions to build a prototype processor. Analog and mixed-signal circuit design of RSFQ circuits. Superconducting electronics and circuit design using Cadence Virtuoso, Schematic Capture, Verilog, VerilogA. Analog Design Tools: Cadence Virtuoso, Implementation Language Cadence Schematic Capture. DAVID J. YVARS GROUP (RAYMOND JAMES - VALHALLA, NY) (2014 2015) Senior Software Engineer - Algorithm Development Invented and programmed Data Mining algorithms for big data analysis to name prospective customers. Programming Tools: Microsoft Visual Studio, Implementation Language C++. COLUMBIA UNIVERSITY SCHOOL OF ENGINEERING AND APPLIED SCIENCE NY, NY (2013 - 2014) Research Assistant in Cybersecurity Research into hardware-assisted cybersecurity methods, unsolvable by software alone. Advisor to team members and co-author of an FPGA prototype of hardware assist coded in VHDL. Digital Circuit Design of FPGA using anti-tamper methods. FPGA Tools: Xilinx, Modelsim, Implementation Language VHDL. IBM RESEARCH YORKTOWN HEIGHTS, NY (2011 2012) FPGA/ASIC Senior Design Engineer High Performance Computing (HPC) Successfully ensured trouble shooting and timing closure of FPGA chips of a massively parallel supercomputer. Named and solved problems with FPGA rack controller, a critical system part. Developed enhanced methods of FPGA ECC and SEU implementation and advised team members with implementation details. Worked in Lab to check waveforms on scope and confirm eye diagrams. Debugged I2C protocol allowing successful operation of the interface between supercomputer nodes. FPGA Tools: Altera, Xilinx, Implementation Languages Verilog/VHDL. 3NORTHROP GRUMMAN BETHPAGE, NY (2009 2011)FPGA/ASIC/Analog Senior Design Engineer Mixed-signal high speed integrated circuits on advanced Bipolar, BiCMOS process technologies using SiGe. Analog IC design including D/A converters, Op-Amps and current sources/ mirrors in GHz range using Cadence for use in electronic warfare systems. Xilinx/FPGA and ASIC design of specialized components using algorithmic implementation: adders and multipliers, FFT for digital signal processing. Set up VLSI digital and analog computing environment for group. Principal Investigator and Project Leader: Nanoelectronics research using Graphene for sensor applications. FPGA Tools: Xilinx, Analog Tools Cadence Virtuoso, Implementation Language, Schematic Capture. LOCKHEED MARTIN GOODYEAR, AZ (2004 2009)FPGA/ASIC Senior Design Engineer Verilog/VHDL Implementation of the Onboard FPU hardware components for a DSP processor used for Space- Based Radar. Invented algorithms for pipe lining FPU design, by employing a novel approach to programmable delay lines. Implemented general purpose data converter between fixed, float and integer data. PRINCIPLE INVESTIGATOR AND TEAM LEADER: Nanotechnology project for adaptation of carbon-based nanotube- based non-volatile RAM (NRAM) for space applications. The NRAM memory successfully evaluated on the Space Shuttle Mission STS-1125 May 2009. Performed analysis and proposed modifications to online chips to mitigate and tolerate radiation damage. Investigated Single Event Upsets as well as structural modifications to hardware on Xilinx chip to enhance rad hardening. With minimal guidance, studies basic design concepts and develops evaluation criteria for evaluating complex systems. Designed and developed a special verification system to debug the number 1 project FPGA/ASIC. FPGA Tools: Xilinx, Model Sim, Implementation Language Verilog. DAVID J. YVARS GROUP AT SOLOMON SMITH BARNEY WHITE PLAINS, NY (2001 2004) Senior Software Engineer Algorithm Development Invented Data Mining algorithms to search customer databases for entities based on learned criteria. Programmed statistical analytical modules in C++ to name confidence criteria of results. Performed IT duties to enhance cyber security of trading systems. Tools: Microsoft Visual Studio, Implementation Language C++ IBM STORAGE AND TECHNOLOGY DIVISION POUGHKEEPSIE, NY EARLY CAREER Advisory Engineer & Research Scientist Pioneered Analog and Digital ASIC I/O design and integration of chips onto the IBM System Z mainframe system control board for multiprocessing, allowing synchronization of loosely coupled processors. Specialized in advanced clocking strategies, clock distribution trees, timing issues and performance optimization for processor to memory interface for IBM System Z. Invented the IBM External Time Reference system architecture which allowed clock synchronization of loosely coupled distributed systems. Enhanced Device Recovery of IBM Fiber/Optical channel by novel architecture design and implementation. Tool: IBM EDS Analog schematic capture for chip design. 4IBM FEDERAL SYSTEMS DIVISION HOUSTON, TEXAS EARLY CAREER Advisory Communications Engineer Team Leader: Space Station Communication between Onboard and Ground Based systems. Author of flight software for Space Shuttle navigation, guidance, and control during re-entry. Tools: TCP/IP, Implementation Languages IBM Assembler Language, ADA, C. AWARDS IBM/NASA Special Commendation Award: Space Station Communication Implementation and Demonstration. Special Recognition Award: Autopilot Guidance, Navigation, and Control of Space Shuttle during Re-Entry, and approach and Landing Tests.TOOLS SUMMARY Engineering Tools: ALTERA, AMS, AutoCAD, AutoCad LT, BIST, Booledozer, CAD, CAD-3D, Cadence, DMA, DRC, Einstimer(IBM), EDS, ESIM, EVE Sim(IBM), GYM(IBM), HDL, HPEESOF, HSPICE, IBM EDS, Magic, MATLAB, Modelsim, Niagara(IBM Layout), Quartus, Questa, ORCAD, PCI, PERL, PSPICE, SPICE, Synopsis, TCL, VHDL, Verilog-AMS, Visio, Verilog, Xilinx FPGA, Xilinx Vivado Suite, System Verilog, VHDL, Schematic Capture, RTL, Planahead. Programming Languages: ADA, Assembler, AWK, C, C++, Fortran, Java, J++, JavaScript, PLAS (IBM), PL1, Python. Operating Systems: AIX, BSD UNIX, Leon, MVS, OS2, Red Hat Linux, Ubuntu UNIX, VM, Windows 10,11. Desktop: Adobe Acrobat, Corel Draw, Microsoft (FrontPage, Excel, PowerPoint, Word). Administrative: ClearCase, Doors.AWARDS IBM - Senior Management Award: Outstanding problem identification and resolution on ES9000 3090 Channel. My efforts allowed the new channel to be completed on schedule. Lockheed Martin -Two Distinguished Service Awards: Digital Logic design and implementation of the FPGA Floating Point Unit (FPU). My design greatly increased the speed and reliability of the FPGA. Lockheed Martin- Executive Commendation Award: White Paper on use of NRAM Nanotechnology for Space Applications. Northrop Grumman - Innovation Challenge Award for the Invention of novel Nanosensor Chip. OTHER ABILITIES With minimal guidance, studies basic design concepts and develops evaluation criteria for evaluating complex systems.Reviews of proposed designs as a developer and project leader. Space Station, Space Shuttle. IBM and Lockheed Martin. Develops Test Procedures and Performs Functional Testing on electronic hardware for radiation testing. Recommended procedures and testing criteria Lockheed Martin Missiles and Space. Prepares and presents electrical engineering materials for Requirements and Design Reviews. Recommended materials for requirements Northrop Grumman, Lockheed Martin, IBM. Applicant makes an extra effort to provide quality internal and external customer service. Always Liaison Actively and effectively participates and contributes in a positive manner. Always Evaluate uncertainty and risks associated with requirements and designs. Bring risks to the attention of management to facilitate their ultimate decision on whether to accept these risks. 5PUBLICATIONS Infrared Electroabsorption Modulation in AlSb/InAs/AlGaSb/GaSb/AlSb Stepped Quantum Wells Grown by MBE, J. Alperin, Q. Du, and W. I. Wang, Dept. Of EE Columbia University, Applied Physics Letters 67(15) 9 Oct. 1995, p. 2218. Normal Incidence Infrared Modulators Based on InAs/GaSb/AlSb Quantum Wells Grown By MBE, J. Alperin, Q. Du, and W. I. Wang, Dept. of EE Columbia University Journal of Vacuum Science & Technology, vol. 14, no 3, p 2343. MBE Growth of GaInSbBi for Infrared Detector Applications, Q. Du, J. Alperin, W. I. Wang, Dept. of EE Columbia University, Journal of Crystal Growth PHONE NUMBER AVAILABLE 849-852. A High Breakdown AlGaAs/GaAs NPN Heterojunction Bipolar Transistor on Si (311) Grown by MBE, J. Alperin, Q. Du., and W. I. Wang, Fellow, IEEE, Dept. of EE Columbia University, Electronic Letters, vol. 33, Issue 19, pp. 1658-1659. MBE Growth of GaAs on Si (511) Using a GaAbSb Amorphous Buffer Layer, Q. Du., J. Alperin, and W. I. Wang. Dept. of EE Columbia University (Submitted 1997). Low Temperature Growth of GaN using InGaN buffer layer by has source MBE, L.K. Li, A. Yang, J. Alperin, and W. I. Wang, Dept of EE Columbia University (Submitted 1997). High Mobility AlGaN/GaN heterostructures grown by gas-source molecular beam epitaxy, L.K. Li., J. Alperin, and W. I. Wang, Dept of EE Columbia University Journal of Vacuum Science & Technology B: Microelectronics and nanometer Structures May 1998 vol. 16, Issue 3, pp. 1275-1277. AlGaAs/GaAs Npn heterojunction bipolar transistors grown on Si (311) by molecular beam epitaxy, Jankovic MJ, Alperin J, Du Q., et al., Journal of Vacuum Science & Technology B, 16(3), pp.1401-1403 (1998). NRAM Memory for Radar Applications, Alperin J., Blissit, J, Lockheed Martin Internal Use Only (2009). Integrated Single Chip Chem/Bio Nanosensor, Alperin J., (White Paper Submitted 2010). |
