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Click here or scroll down to respond to this candidateCandidate's Name Email: EMAIL AVAILABLE
Mobile: PHONE NUMBER AVAILABLE
Education
Iowa State University Ames, IA, USA
Doctor of Philosophy - Computer Engineering; GPA: 3.Street Address July 2016 - July 2023
Sastra University Thanjavur, TN, India
Master of Technology - VLSI Design; GPA: 3.55 July 2011 - May 2013
Anna University Nagapattinam, TN, India
Bachelors of Engineering - Electronics and Communication Engineering; GPA: 3.35 July 2006 - Dec 2010
Skills Summary
Languages: C, Verilog HDL, System Verilog, UVM
Simulation Tools: Mentor Graphics Questa, Synopsys VCS, Logic Analyzers, Digitizer Card
Synthesize Tools: Synopsys Design Compiler, Fusion Compiler, Xilinx Vivado
DFT Tools: Synopsys DFTMAX, TetraMAX, SPYGlass DFT ADV, Verdi AMS Debug
Scripting: Python, Shell scripting, TCL, SKIL
Other Softwares: Matlab, SPICE
Hardware: RTL Coding, Silicon Validation, Verification, DFT, FPGA Design
Soft Skills: Leadership, Communication, Powerpoint Presentation, Technical Writing
Experience
CloudData Technology Ames, Iowa
Hardware Engineer Oct 2023 - May 2024
Designed and tested new integrated circuits and hardware components for various signal processing applications.
Implemented and evaluated signal processing algorithms on FPGA and ASIC platforms to ensure robust and reliable
performance. Conducted extensive simulations and testing to validate the functionality and performance.
Developed and documented firmware for digital signal processors. Optimized code for performance, efficiency, and
reliability, ensuring seamless integration with hardware components.
Collaborated with cross-functional teams to ensure modifications met stringent performance and reliability criteria.
Documented all modifications and adaptations, ensuring compliance with government standards and protocols.
Synopsys Inc. Mountain View, California
Technical Engineering Intern Aug 2022 - Jun 2023
Contributed to developing and validating technology libraries, ensuring functional specification accuracy, and
coordinating seamless EDA tool flow updates.
Conducted comprehensive testing against security threats and implemented SCAN/JTAG test methods, collaborating
with design teams to integrate DFT methodologies into ASIC designs.
Led the development and execution of ATPG for manufacturing tests, optimizing test data through gate-level
simulations for efficiency and coverage.
Developed and executed DFT validation plans, focusing on hardware security logic, and used formal tools for structural
equivalence checking and Silicon Validation.
Iowa State University Ames, Iowa
Graduate Research Assistant Sep 2016 - Jun 2022
Investigated the on-chip power distribution network using Cadence Virtuoso to enhance resistance against side-channel
attacks. Implemented security-aware PDN routing strategies, employing SPICE simulations to validate the effectiveness
of the countermeasures.
Designed a versatile decoupling unit for seamless integration into semi/full custom design processes. Utilized TCL scripts
to automate and optimize the design flow, ensuring efficient and secure PDN routing.
Led the development of RNS-based secure logic for cryptographic applications, integrating Homomorphic Encryption
techniques to enhance security. Explored a hybrid solution integrating RNS with secure-aware power routing using
decoupling capacitance.
SETS Chennai, India
Project Associate Jun 2013 - Jun 2016
Conducted a quantitative study to evaluate the impact of transparency order on decomposed S-Boxes to enhance
resistance against side-channel attacks.
Led the R&D project of a robust power model to assess side-channel resistance in FPGA implementations.
Executed comprehensive experiments to evaluate the effectiveness of countermeasures against potential side-channel
attacks. Utilized oscilloscopes and logic analyzers to measure and analyze power consumption, ensuring accurate data
collection and interpretation.
Projects
Inimical Hardware Detection
Funded by Collins Aerospace 2022
Designed a ring oscillator-based power stream sensor to monitor power variations indicative of potential security threats.
Integrated the sensor system design on a reconfigurable hardware platform, ensuring adaptability and ease of deployment.
Collected extensive power stream data and preprocessed it for training and testing machine learning models. Trained
various models to identify and classify patterns associated with security threats, optimizing them for accuracy and
performance. Demonstrated seamless integration of the detection system on a reconfigurable platform.
Decoupling Monitor Unit for Board-level Trojan Identification
Funded by DARPA 2021
Designed and implemented a decoupling monitor unit to track and analyze board-level activities, specifically targeting
Trojan detection. Integrated the monitoring unit with Zynq SoC, ensuring seamless communication (PCIe and Ethernet)
protocol development and synchronization of program execution across the board.
Utilized LSTM networks and RNN to analyze patterns and detect anomalies indicative of Trojans. Gathered extensive
operational data from the board-level activities and preprocessed it for training/testing the neural network models.
Develop and Validate SCA Countermeasures
Funded by SRC 2020
Integrated t-private circuit and Residue Number System (RNS) secure logic into the AES algorithm.
Employed SPICE simulations to evaluate the effectiveness and reliability of the implemented countermeasures.
Quantified the performance overhead introduced by the countermeasures through detailed simulation and analysis.
Gathered simulation data to assess the trade-offs between security enhancements and performance impacts.
Publications
Selvam, R., Tyagi, A. Residue Number System (RNS) and Power Distribution Network Topology-Based Mitigation of
Power Side-Channel Attacks. Cryptography. 2024; 8(1)
Selvam R., Tyagi A. A Side-Channel Evaluation of On-chip Vdd Distribution Network with Decoupling Capacitance. SN
COMPUT. SCI. 2023; 77(4).
Selvam R., Tyagi A. An Evaluation of Power Side-Channel Resistance for RNS Secure Logic. Sensors. 2022; 22(6).
Selvam R., Tyagi A. Power Distribution Network Capacitive Decoupling for Side-Channel Resistance. IEEE International
Symposium on Smart Electronic Systems (iSES), Jaipur, India. 2021, pp. 183-188.
Selvam R., Tyagi A. Power Side Channel Resistance of RNS Secure Logic. 2018 31st Inter. Conf. on VLSI Design and 2018
17th International Conference on Embedded Systems (VLSID), Pune, India. 2018, pp. 143-148.
Selvam R., Shanmugam D., Annadurai S., Rangasamy J. Decomposed s-boxes and DPA attacks: A quantitative case
study using PRINCE. 2016 Lecture Notes in Computer Science, Security, Privacy, and Applied Cryptography Engineering
(SPACE), India. 2016 pp. 179-193.
Selvam R., Shanmugam D., Annadurai S. Vulnerability Analysis of PRINCE and RECTANGLE using CPA. 2015
Proceedings of the 1st ACM Workshop on Cyber-Physical System Security (CPSS), Singapore. 2015 pp. 81-87.
Shanmugam D., Selvam R., Annadurai S. Differential Power Analysis on SIMON and LED Block Ciphers. 2014 Lecture
Notes in Computer Science, Security, Privacy, and Applied Cryptography Engineering (SPACE), India. 2014 pp. 110-125.
Leadership and Volunteer Experience
Sankalp Ames, Iowa
Daawat Coordinator Mar 2017 - Feb 2022
Reviewed budgets proposals of several non-profit organizations from India and secured funding for the same by
hosting an annual fundraising dinner.
Successfully conducted 2 fundraisers and raised over 5000$ to aid COVID-19 patients in India.
Volunteered at tree plantation drive and free meal program in our local community.
ECE Department Students Association (SPARKS) Nagapattinam, India
President Aug 2008 - May 2010
Organized a national level technical symposium (Inferno 2K10) and extracurricular events including inter-
college sports events and cultural.
Created yearly agendas, facilitated department meetings, coordinated the committee members, and delegated
the tasks to fulfill the association s agendas.
Collaborated with Rotary Club to organize a blood donation camp on campus.
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