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Click here or scroll down to respond to this candidateCandidate's Name
Street Address Vincent Avenue SouthMinneapolis, Minnesota USA Street Address
PHONE NUMBER AVAILABLEEMAIL AVAILABLESUMMARYPhysical Design and Analog Layout Engineer with experience in design of complex ASICs including Analog/Mixed Signal circuitry including PLLs, DACs, memory test circuits, preamplifiers, circuitry for neuromodulation deep brain stimulation and Medtronic leadless pacemaker circuitry.Versatile integrated circuit mask designer with over 15 years of experience.Skill spans all aspects of the design cycle from low-level transistor layout, circuit layout, floor plan design, chip level layout and mask procurement.Able to work independently, or as a team member in a lead or a supporting role.Experienced in sensor (infrared microbolometer) manufacturing and testing.Circuit TypesoDeveloped ASICs including Analog/Mixed Signal circuitry including PLLs, DACs, memory test circuits, preamplifiers, IO pads, PCM (Process Control Monitoring), PPG, blood pressure monitoring circuitry.TechnologiesoDeveloped in CMOS, BiPolar, SiGe, microstructure technologies such as solid-state lasers, infrared detectors and emitters, linear arrays and pressure sensor.ToolsProficient in many simulation and layout tools including Cadence and Mentor GraphicsEXPERIENCE2021-2024: IC Mask Designer, Medtronic, Mounds View, MinnesotaIC Analog Layout:Worked in a development team that was chartered with development of neuromodulation deep brain stimulation devices, Medtronic leadless pacemaker circuitry and implantable monitoring devices.Supported Medtronic Cardiac Rhythm products were developed using 55nm and 250nm technology for their LINQ, LINQII monitoring (capture atrial fibrillation sends all relevant heart rhythm data to physician) and Micra leadless pace marker products.Supported Medtronic neuromodulation deep brain stimulation products that were developed using 250nm technology.Excellent communication skills and able to work with cross-functional teams.CMOS technologiesUnderstanding of analog design best practices.Had lead role; facilitate team communication through IC layout meetings.Medtronic recognition program:oReceived recognition for the successful completion of blood pressure layout design before the fracture date.oReceived recognition for our outstanding teamwork and collaboration that lead to the successful achievement of our tape-out deadline for the PCM (Process Control Monitoring devices/features).Tools and Software:SVN repository that is used for version control system.Cadence Virtuoso IC Layout software to create trusted analog designs.Used Polarion software to track status of layout projects.Proficient in Cadence PVS/Mentor Graphics Calibre verification tools such DRC, LVS, ANT and FILL (Metal utilization).Proficient in debugging and interpreting results using the PVS short checker software.2014-2021: Physical Integration Design Engineer, Micron, Minneapolis, Minnesota2014-2021: Physical design Micron TechnologyWorked in a development team chartered with development of integrated circuits designed to test memory chips. Used a multistep standardized design process that consisted of pre-place, place, clock optimization, nano-route, and ECOs. The process involved iterating between cell-level and partition-level designs, Used the following design tools and processes:Timing analysisoStatic timing analysis (using Tempus)oClock setup and holdoTiming closureCalibre: for DRC/LVSVoltus: for static power analysisInnovus: for the whole flow:oNano-routingoFor ECO (Engineer Change Order) managementSVN: for file organization/tracking changesTCL programming language: For scripts to automate process steps2004-2014: IC Mask Design Engineer, Agere/LSI/Avago, Mendota Heights, Minnesota(LSI was acquired by Avago in 2014)(Agere was acquired by LSI in 2007)Physical design:Led IP and customer development for disc drive writer, reader, and subsystems (temperature compensation, proximity sensing, etc.)Successfully achieved 100% product execution score card for product quality and early time to market from the companys largest customer.Core member a team that developed preamplifier products that secured 51% market share for the company.Conducted investigations of the best practices to capture chip level critical net parasitic.Led and supported integration of all circuit blocks so they functioned as a complete disc drive preamp system for existing and new technologies.Signal path matching, line shield protection, critical net optimization, well proximity effects were always taken into consideration when planning out cell, block, slice and chip level routing.Successfully achieve schedule, cost and die size requirements for complex designs.Experience in chip floor planning, pad negotiation and schedule estimation.Used SiGe process rules with Cadence Virtuoso and Mentor Calibre.Used Bipolar, CMOS technologies with various types of matching, quad coupling, inter-digitation and shielding techniques.Developed a wide variety of designs (digital to analog converters, digital designs, voltage regulators, comparators, filters, multipliers, and current reference as well as other IP building blocks.)Supported various technologies such as Com3/SiGe and Com3Plus/SiGe for WD/Seagate Pre Amp products.Addressed mask procurement including order entry, data transfer, and coordinated communication with stakeholders (project management, design, mask vendors, etc.)Simulation:Supported preamp designers in the following areas (electro migration, Check ESD, Crosstalk Parasitic Capacitance Analysis, resistance/capacitances on critical nets, terminal to terminal resistance values, Apache Totem IR drop analysis).Verification:Supported the verification team in various activities such as testing Cadence constraint driven layout features for modgens, differential pairs and symmetry.Teamwork:Demonstrated good communication skills working with team members located in Longmont and in Shanghai.Developed a good working relationship with the mask design engineering team.Very flexible to meet engineer needs and project schedules.Trained new layout personnel in proper layout techniques and methodology. Trained new Physical Design Engineers/Engineers in cell, block and chip level construction.Customer Focus:Flexible during design changes and reliable regarding schedule deadlines.Maintained or exceeded customers tight tapeout schedules.Tools:Led customer-focused efforts for preamp sub-circuit and chip level layouts using verification tools such as Cadence OA, Calibre, Mentor Graphics LVS/DRC, etc.Used Assura and Calibre verification with Cadence. Experience with Auto routers (Vcar,VSR) to route block and top level designs.Cadence Virtuoso XL Layout and Schematic editor, Calibre and Assura DRC and LVS, Totem Apache.Used Agile documentation system to meet ISO requirements for documentation retention.Utilized a SharePoint system for archiving documentation.Volunteerism:Lead role for a group of LSI employees in helping serve breakfast to the homeless at the Saint Paul Salvation Army.Coordinated a group of volunteers to perform tasks at the Women Shelter in Saint Paul for volunteer week.Participated in helping LSI be recognized in the community by participating in making lunches for a homeless shelter and filling bags full of food for the Feed My Starving Children2000-2004 Design Technician, LSI Logic, Bloomington, MinnesotaPerformed analog circuit layout such as custom and library PLLs (Phase Locked Loops) and Digital to Analog Converter (DAC) circuitry. Obtain schematics, layout of all sub-circuitry, assemble all sub-circuitry to produce complete circuit layouts. Performed verification at both sub-circuit and top level, created frameview(s) for LSIs Physical Design Center, provided LPE (capacitance extraction) data to support closed-loop simulation efforts. Conducted electromigration and signal balancing analysis by using Calibre verification decks.Had sole responsibility for layout of five PLLs, with nineteen total circuit variations; created all test frames and custom layout structures. The proper function of analog circuits is exceedingly dependent on layout---circuit capacitance and balancing must be carefully controlled. All PLLs met or exceeded performance across all test conditions and resolved several customer issues such as dither lock and electromagnetic interference. These PLLs were key to LSIs vertical markets and external customers.Performed layout of digital circuitry on a wide variety of custom and library I/O buffers, reference, ESD and various support cells. Rapid metal programmable I/Os, standard cell(s) layout assignments across multiple technologies.Excellent abilities to work with digital designers to understand the unique custom PCIX2.0 I/O architecture requirements. I/O and ESD rules as well as new verification checking tools. Excellent in responding to a myriad of fast turn layout iteration requests that were required to keep both the PCIX2.0 project and the Phoenix test chip development effort on track and avoid schedule delays.Lead layout mask designer for a massive ESD failure on the entire .18 mm rapid metal programmable I/O library (63 cells) which needed to be updated. This project had high visibility on a short timeline. Worked from a list of prioritized updates based on customer needs to deliver updates on time per target commit date. Note: all information was made accessible prior to the start, enabling me to be very efficient in completing updates and resulting in me being able to deliver the updated layout on schedule which enabled others to be successful in meeting their commit dates.Layout efforts supporting both PLL and I/O groups.Worked with the verification team by helping them build regression cells to use to verify DRC rules in multiple technologies.Supported PLL/IO designers in areas beyond the normal realm of mask design (extraction, GEN, FRAM view generation, check-in).Performed physical layout of integrated circuit cells using Mentor Graphic tools according to design schematics, design rules and fabrication process rules.Obtain, review and interpret integrated circuit cell schematics, net lists and related information.Discussed and resolved design and layout sensitivities with local and remote engineers.Responsible for modification of existing cells or generation of new cells from scratch; some involved a single cell or more complex blocks of cells and circuits.Proficient in layout and floor planning of custom cell transistor-level layout.Mentored and supported new mask designers to help them learn tool flows, verification and methodology.Very knowledgeable with architectural rules for standard I/Os, PLLs, and rapid chip technology (gate arrays).Excellent in interpreting schematics, technology rules, documentation, and design rules.Proficient with Avant software for generating/viewing frameviews for various designs (I/Os, hardmacs.)Superior knowledge with Viewdraw software to view, edit, and generate net lists (flat or hierarchical) from schematics.SKILLSProficient in verification tools such as Calibre, JCRules, Mentor IC Station, DRC, LVS, LPE, LADR, (checks top-level layers), MU (Metal utilization.)Very experienced in Candence and Mentor Graphics software.Knowledge/experienced in Construct, L-Edit, OrCad, UNIX, Hyperplot, Dracula, Unix based Sun workstations, Windows, Macintosh, PC, Excel and Word.Experienced with Avant software for generating frameviews for various designs (I/Os. hardmacs).Excellent with Powerview/Viewdraw software to view, edit, print and generate net lists (flat or hierarchical) from schematics.Proficient in UNIX commands and workstation operation.Interpersonal behavior and skills: ability to prioritize and plan workload to meet delivery schedules.Interfaces well with engineers and other groups to resolve issues such as layout technology and verification.Ability to handle multiple tasks and projects simultaneously.1984-2000 Research Technician, Honeywell, Plymouth, MinnesotaWorked in research at Honeywell Technology Center (1987-2000) and in production at Honeywell Solid State Electronics Center (1984-1087)Fabrication and layout of various micro-structures such as semiconductors lasers, infrared detectors and emitters, linear arrays and pressure sensor devices. Focused on detailed device specifications to address all quality issues before layout. Maintained accurate documentation of work performed.Handled several projects simultaneously; ensuring assignments were done in a timely manner.Communicated effectively with engineers on all phases of design process form initial design, design reviews, mask procurement and mask acceptance.Coordinate with mask vendors to provide timely service and turnaround.Member of a design team to evaluate various design software packages and to make recommendations to management on procurement.Assist engineering in the development and implementation of new integrated circuit and microstructure manufacturing processes.Review and update operating procedures and kept control logs on product specification.Coordinate the processing of infrared detectors and emitters.Acted as liaison for transfer of infrared micro-bolometer technology to external customers. Provided training and technical processing support needed by technology transfer engineers.Established cohesive team relationships.Assisted in device testing and packaging.IC process technician on advanced packaging technology; this included operation and maintenance of various pieces of processing equipment and coordination of process flows.Performed in-process and post processing tests on devices and circuits. This utilized testing equipment such as oscilloscopes, HP testers, and probe stations. This included noise measurement (Johnson noise) on infrared sensors.Assisted in successful intra-divisional transfer of thin film multilayer packaging technology.Wrote operating processes for thin film multi-layer (TFML) packaging and tested the packaging technology.Worked with engineering and process control to ensure customer requirements were met in a timely and cost-effective manner.EDUCATIONBachelor of Arts in Marketing, 1995 Metropolitan State University, Minneapolis, MinnesotaAssociate of Arts, Electronics, 1988, Minneapolis Technical Institute, Minneapolis, MinnesotaAssociate of Arts Liberal Arts, 1992, Normandale Community College, Bloomington, Minnesota |
