| | | 20,000+ Fresh Resumes Monthly | |
|
|
| |
Click here or scroll down to respond to this candidateCandidate's Name
PHONE NUMBER AVAILABLE EMAIL AVAILABLE ;Street Address
Senior Design & Verification Engineer Technology leader with over 10 years of software and hardware development expertise managing entire design process from initial concept through planning to maximize efficiency and minimize risks. Core strengths include: Programming/Coding/Scripting Circuit Timing/Design/Analysis Debugging SoC Verification/Validation Gate Level Simulation Embedded Systems/Software/Hardware FPGA Design PrimeTime STA Digital Signal Processing Pattern/Vector Generation Object Oriented Development Excel Macros ATPG TestKompress Web Server/Development/Graphic Designs Project Management/Planning Scripting Python PERL XML SED AWK Design & Verification Verilog, VHDL, SystemVerilog, Vera, ABV, UVM, SPW, Simulink, (SVA, PSL Assertions Operating Systems- Windows, Linux, UNIXProcessers- x86, ArmHardware- FPGA (Lattice Diamond, Altera Quartus, Xilinx), Various Emulators/Accelerators Software- C, C++, C#, Perl, Python, TK/TCL, R, Javascript, Matlab Analysis- OOD, OOA, Lifecycle, Logistic, Static Timing Analysis Tools- Cadence, RTL Compiler, Visual Studio, Modelsim, VCS, NC-Verilog, NC-Sim, Virtuoso, Aldec, git, Node, NPM Major ContributionsImplemented cHDLC DVB-S2 baseband framing encoding (modulator FPGA) and decoding (demodulator FPGA) for the L3 SLM5650-B DVB-S2 modem; it supports REG LEG, LEG REG CCM and ACM bridge mode operation as well as point-to-point switch operation.Performed mixed signal verification of PMIC controllers multiple rail BUCK converters and LDO regulators and single rail multi-phase PWM. Conducted verification analysis and task breakdown. Transformed tasks into simulation stimulus to verify PMIC operation for RTL, gate level, and top-level AMS simulation as part of the tape out flow. Developed and integrated Perl program into graphics core Cherryview scan validation flow; saved two engineering resources and significantly increased in pattern volume space for validation, going from team of three validating 162 patterns collectively to one engineer generating and validating 3,467 in later project stepping. Quickly found and root-caused showstopper bug contained in entire 54 partitions of the graphics core; avoided schedule impacts and delays for the Cherryview next stepping. Performed, managed, signed off and delivered final project for LBIST collaterals and scan PV timing closure for graphics core in Valleyview (Bay Trail) SoC, helping company meet goal of over 40 million unit sales; exceeded Bay Trail graphics core test coverage requirements for LBIST by over 91%. Attained customer production objectives of 800+ units per month, resulting in over $2M in revenue for production run; overcame issues related to test equipment/fixture calibration and procedure documentation, production software readiness/release, training personnel to run tests and analysis of failed products. Eliminated over $1M in mask cost charges, introduced first-pass release success and cut design cycle time by over 30% by taking integral role in establishing project conventions for SoC IC design, which defined standard design practices for variety of key processes.Career OverviewApex Semiconductor/ Static Controls August 2020 March 2024 Reversal Engineer Utilize Hierux image gate extracted netlist as a starting point to accurately uncover and model the operation of HP and Sharp printer controllers for secondary ink cartridge market. Developing Verilog simulations using the extracted gate netlist to determine controller operation and uncover the type of microcontroller and set of instructions used by the printer. Perform analysis on various camouflage cells to determine their functionality so they can be accurately represented in the netlist. Developing a python program/ script to validate the ARM 16, 32, and 48 bit instructions that have been identified as well as any new instructions that may be discovered; and generate ARM assembly instruction code for software engineers.Comtech EF Data April 2018-April 2020Engineer II FPGA design, implementation, and verification of LM5650-B and Heights satellite modem product derivatives based around Altera Aria FPGAs and the Quartus design environment. Designed and integrated cHDLC baseband encoding and decoding portion of the LM5650-B modem modulator DVB-S2 waveform. Additionally implemented the demodulator decoding as well as a high-speed serial transceiver between RX and TX FPGA to support ACM operation. Adapted and integrated existing IP spreading block from the LM5650-B modem into the Heights remote modem modulator Developed PWM controller for the Heights back-plane hub chassis bay cooling fans on a Lattice X02 FPGA using the Diamond design environment.ON Semiconductor Jan 2016-March 2018Mixed Signal Verification Engineer Managed mixed signal verification, perform digital and top level verification of various mixed signal PMIC controllers. Perform verification analysis and task breakdown. Developed and modified Verilog AMS/ SV analog models for various simulation abstractions. Implemented One Time Programming (OTP) functionality using Verilog allowing PMIC factory configuration. Conducted simulations using Virtuoso to verify coverage and expected performance against verification plan. Verified and debugged PMIC part functionality on engineering lab bench. Assisted test engineers on PMIC part configuration, bring up, and debug on automated tester Intel 2011-2015Graphics Hardware Engineer Implement TestKompress EDT scan solution for graphics core portion of Cherry Trail SoC, validating stuck-at and at- speed generated patterns in post-synthesized scan-inserted simulation environment, and performs timing closure analysis prior to handing off pattern deliverables to manufacturing and test engineers. Installed graphics level LBIST architecture with TAP and managed integration of all 15 partition level collaterals; responsible for graphics core level pattern generation, pattern verification and overall scan timing closure, developing and validating STCL scripts to fix timing in max corner. Delivered B0 and C0 steppings in alignment with corporate PRQ and refresh cycle goals with more than 14 million product shipments in 2013.Jabil 2010-2011Test Development Engineer Directed development of functional test verification and validation for electronic hardware/software assemblies in lean manufacturing environment; achieved 100% functional test coverage for Clinac Medical Scanning device with enhanced capability, allowing production programming as part of functional test. Designed and implemented hardware/software test fixtures in accordance with verification plans, utilizing Object Oriented Visual C++ .net managed framework for test software to achieve highly integrated, automated and robust environment requiring minimal test operator interaction or involvement. Freescale Semiconductor/Motorola SPS 2007-2008Senior Technical Staff Engineer/APD Technical Design Lead Boosted performance speed up to 50% for Adaptive Pre-Distortion (APD) system by executing digital architecture, design and functionality to incorporate lookup table (LUT) based DMA engine to allow APD training and updates without ARM processor intervention under certain scenarios. Accomplished APD system improvements by designing framework and methodology that enabled effective management of diverse areas of entire APD digital pre-distorter and system; defined implementation approach via diverse trade studies, and established and monitored APD schedule and task allocation. Adapted to constantly changing system requirements through proactive efforts, process mapping and cooperation with other engineers in order to meet targeted schedule goals. Senior Staff Engineer/Audio Transceiver 2007 Integral in development of synchronous audio test chip, coordinating deployment of integrated class D audio transceiver intended for use in power management solutions; completed design, RTL coding, test bench development and verification for equalizer, CIC filter and virtual 3D blocks digital signal processing blocks (DSP). Uncovered 30% current reduction in asynchronous design versus synchronous design by establishing baseline for system level performance for synchronous Verilog RTL and gate level simulations; implemented two different architecture design approaches in parallel in attempt to save overall power in audio lineup. Produced bit-exact Matlab Simulink-based fixed point model to generate test vectors used for both RTL and gate level simulations, using VCS simulator to perform validation for release to FAB. Senior Staff Engineer/RF-IF Transceiver Design Engineer 2005-2007 Built, evaluated and translated high-speed bi-directional DigRF3G bus interfaces, ensuring achievement of timing/interface requirements by applying architectural specifications to create transmit path 3G digital filtering. Developed Vera Transactors for high level test verification and utilized VCS to accomplish gate level simulations and validate HSIO interface. Oversaw release of Python MMM7210 2G/3G transceiver for Motorola mobile phones; standardized IC development processes by establishing project convention guidelines. Launched 3G transmit data path filtering (SRRC, Lagrange, interpolation) by developing, implementing and verifying Python application, as well as verifying Python DigRF 3G interface. Staff Engineer/Power Management Design Lead 2002-2004 Led overall digital tasks for coordinating design and deployment of audio codecs, power control and SPI digital modules; analyzed algorithms, programmed power management control RTL, and created analog and mixed signal modules for top level SystemVerilog test bench. Initiated extensive set of power management use cases for power-on sequencing of various regulators, successfully anticipating new customer usage model and incorporating necessary logic as backup; had zero impact to schedule and zero increased cost when customer requested changes to accommodate new model. Credentials MS, Electrical Engineering/Communication Systems & Signal Processing Arizona State University BS, Electrical Engineering University of Utah Training/Certifications Embedded Systems - Edx.org System Verilog - Udemy Python - Edx.org/Team Treehouse C++ - Programmr.com |
