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Candidate's Name  1Alan GeistPHONE NUMBER AVAILABLE EMAIL AVAILABLEPortland, OR LINKEDIN LINK AVAILABLELOGIC DESIGN ENGINEER - HARDWARE DESIGN ENGINEERInnovative, inventive design engineer with experience in hardware and logic design engineering. Expertise includes: High speed logic design  Synchronization/Metastability PCIe, Bluetooth, WiFi, DO-181E, & more Signal Integrity Circuit board and connector technology Programmable Logic FPGAPROFESSIONAL EXPERIENCEFirstPass Engineering (purchased by Synopsys Inc. during tenure) 2019-2024 Principal EngineerMicro-architecture, logic design, debug, documentation. Micro-architected, implemented, and debugged multiple blocks for a large HDM controller for a massively parallel supercomputer. Became the go-to guru for System Verilog implementation questions and synchronization issues. Was a primary author for the departments methodology guide, including authoring much of the coding guidelines and RDC (Reset Domain Crossing) chapters, and sole author on CDC (Clock Domain Crossing) chapter. Taught a very well received class on CDC theory and methods during some project downtime. Submitted five inventions for patent, three of which were/are being pursued by the company.Sagetech Corporation, White Salmon, Washington 2016-2018 Senior Digital Design EngineerRTL design for aviation transponder and rangefinder. Designed, debugged, and documented several logic blocks for an FPGA-based on- board, low-power, low-volume aviation rangefinder. Later did the same for an aviation transponder in the same package. Submitted an invention disclosure for a novel mesochronous synchronization solution. Aided the FAA certification effort for the transponder. Mentored several less-experienced logic design engineers. Received strong reviews for my efforts. Reference available. Authored the RTL coding guidelines for the company also to strong reviews. Candidate's Name  2Lattice Semiconductor, Hillsboro, Oregon 2014-2015 Staff Digital Design EngineerRTL design for FPGA configuration logic. Micro-architected, implemented, and debugged multiple blocks for a new generation FPGA. Blocks included I2C slave interface, SPI master/slave interface, synchronizing FIFO, and power-up self-test. Submitted an invention disclosure for a reduced-noise bus signaling protocol. Worked to help evaluate and bring up a new CAD tool suite and the associated compute environment.Intel Corporation, Hillsboro, Oregon 1991-2014Senior Component Engineer, 2006  2014Provided micro-architecture and logic design engineering for several Many-Integrated- Core (MIC) processors. Micro-architected, implemented, and debugged an interface to a PCI Express endpoint. The module had data flow in six different directions with arbiters at each output. Also had multiple clock domains, error logging and recovery logic, and significant flexibility achieved through programming. Invented and patented a method for synchronization of data between asynchronous clock domains. This method had the desirable feature of being repeatable in a debug environment, in spite of being inherently non-deterministic. It saved many person-hours of clocking design over prior deterministic solutions. Helped engineer a combination DDR controller/embedded DRAM based cache controller for a many-integrated core processor. Coded the interface to main internal network, added features, and helped debug the overall design. Senior Component Engineer, 2004  2006Micro-architecture and logic design engineer for three wireless communication ICs. Upgraded a pre-existing Medium Access Controller (MAC) from Bluetooth 1.1 to Bluetooth 2.0. Added new packet types, a new interface between the MAC and physical layer, and upgrades to several state machines and other control logic. Team member for an ongoing 802.11a,b,g physical layer design. Evaluated existing designs from another Intel group, and made recommendations. Performed RTL implementations. Engineered a highly generic, reusable, and efficient decimation filter, such that the tap count, coefficients, and word widths could be specified later. Part of a team that converted a pre-existing design from Intel process to an external process. Created numerous scripts used for making gate-level simulation models of the design.Candidate's Name  3EDUCATIONBachelors of Science in Electrical EngineeringCase Western Reserve University, Cleveland, OhioPATENTSData transfer between asynchronous clock domains.Patent number WOPHONE NUMBER AVAILABLE A1. Awarded July 4, 2013. Apparatus and Method for Automatic Matching of Signaling Rise Time to Fall Time. Patent number 6,362,672 B1. Awarded March 26, 2002. Method and Apparatus for Integrated Local and Express Routing in a Multiprocessor. Patent number 5,546,596. Awarded August 13, 1996.Two new inventions with patent applied for or in process for filing, but not yet public information. All are related to novel synchronization schemes. PUBLICATIONSA New Method of Cross-Domain Synchronization with Repeatability Published at Intel Design, Test, and Technology Conference (DTTC), August 2009.Measuring Crossing Voltage for Differential Signals Published at Intel Validation Summit/DTTC. Fall 2000. Became the preferred method in several large verification groups.