| | | 20,000+ Fresh Resumes Monthly | |
|
|
| |
Click here or scroll down to respond to this candidate4131 E Shea BlvdPhoenix, Arizona Street Address
PHONE NUMBER AVAILABLEEMAIL AVAILABLECandidate's Name
Career ObjectiveTo secure a position where experienced contributions add immediate value and acute learning drive career advance.ExperienceCanaan CreativePhoenix, AZ June 1, 2022November 30, 2023Principal RTL Design EngineerRTL design owner of LPDDR{4,4x,5} RiscV memory controller for ASIC SoC targeting AI-centric end productsCapgemini/Facebook/MetaPhoenix, AZ June 2021May, 2022Principal RTL Design EngineerRTL design owner of Triangular Solve Engine with pipelined parallel floating-point accelerators targeted for next generation Oculus VR ASIC implemented in 5nm Samsung process technologyHoneywellPhoenix, AZ November, 2020May, 2021Principal Semiconductor EngineerCreated UVM random testbench environment to demonstrate robust immunity to a wide range of transient noise eventsCompleted testbench scoreboard matrix demonstrating correct FPGA behavior across thousands of unique testpointsPresented verification results to Boeing as well as participate in weekly customer meetings on flight control systemsCompleted complex task of formal verification for legacy netlist without synthesis guidance svf which I created manuallyMercury SystemsPhoenix, AZ November, 2019October, 2020Principal FPGA Design EngineerFPGA design of secure SSD architectures for mission critical terrestrial and space applicationsIBM Microelectronics(Acquired by GlobalFoundries) Contract via Encore Semi Phoenix, AZ January, 2015November, 2019SerDes Design EngineerPhysical implementation owner of 112Gbps LR/XSR SerDes blocks in TSMC 7nm Cadence innovus flowtoolOwner of synthesis timing closure/signoff of LR and XSR SerDes blocks pre/post physical designHardware lab bring up of 112Gbps SerDes core implemented in GF 14nm process technologyWrote Lua algorithms and Python BER eye-diagram code for 112Gbps core and FPGA hardware verificationRTL design owner of 112Gbps SerDes RxLinkLogic algorithms including Mueller-Muller CDR, 32-tap FFE, CTLE/peaking implemented using Cadence tool flow in GF 14nm with interface to Xilinx FPGA that included Reed-Solomon FEC, PAM4 pattern generator and checker implemented using Vivado toolsRTL design of Dynamic Data Centering Rx algorithm for 56Gbps products in 14nm GF process technologyCreated Carry-Save Adder models at higher-level of abstraction significantly reducing simulation timeWrote testbench code in systemVerilog for individual ADC, LTE, DFE, FFE and CDR blocks as well as system-level rxCoreLogic testbenches to verify both the 112Gbps ASIC and FPGA implementationsIntelChandler, AZ October, 2013October, 2014Component Design EngineerContributed to the 2nd Generation Fuse Controller Chassis IP including design/documentation updates and script/tool infrastructure creation improving automation, efficiency and quality of IP deliverables to product teamsIntelChandler, AZ April, 2011October, 2013Component Design EngineerDesign owner of SerDes Tx High Speed Serial I/O RTL written in System Verilog in Intel 14nm processCreated UPF solution for NLP power-aware simulation and synthesis of multiple power-gated logic partitionsCreated synthesis constraints for multiple clock domains meeting timing requirements up to 3GHz using Primetime STA and regression testing GLS with back-annotated SDFExperience with a variety of validation tools including VCS/DVE, Verdi, Lintra, Spyglass, CDC, Fishtail, LECAuthored TX Logic Architecture Specification, Test Plan and whitebox assertionsIntelChandler, AZ December 2010April 2011Design/Verification EngineerVerified complex media SoC design blocks using OVM on System-Level Emulation Palladium targetsCreated and verified new complex top-level media SoC IP block configuration using OVM test environmentIntelChandler, AZ May 2010December 2010Digital Design EngineerDesigned massively parallel vector memory controller including load/store pipeline to reconfigurable systolic array of compute engines, aggregation cache and arbitration protocol for three different split transaction bus interfacesFreescale(formerly Motorola Semiconductor Products Sector)Tempe, AZ 20052007Senior Staff TechnologistCreated 68K/ColdFire core and platform RTL deployments for successful IP licensing with customersHosted webinar for Freescales V2 ColdFire core platform IP available licensing @ ip-extreme.comDesigned reusable testbench infrastructure deployments enabling seamless verification by customersDeveloped RTL build, sim & synthesis scripts (Synopsys/Cadence front-end flows) deployed with soft-IPAuthored technical specifications required to integrate licensed IP with customer ASIC/SoC productsMotorolaTempe, AZ 20042005Staff Digital Design EngineerTechnical manager of 5 direct report engineersIndividual design contributor of reusable core-agnostic Standard Product Platform (SPP) blocks implemented in high-volume automotive and consumer electronic SoC productsMotorolaTempe, AZ 19982004Senior Microprocessor Design EngineerDesigned instruction result forwarding optimization within the Operand Execution Pipeline (OEP) of V4 ColdFire Embedded Core productsDesigned reusable byte-sliced datapath structures to optimize synthesis implementation within 64-bit superscalar micro-architecture of V5 ColdFire Core productsPerformed extensive performance analyses over the years using EEMBC, customer and internal application code to benchmark competitive advantages of specific ISA solutions (68K/CF, ARM, PowerPC) versus competitors, e.g., MIPS targets included core architectural models, ISS, Verilog and siliconDeveloped lint program, written in Perl, which verifies all Verilog source design files comply with reuse standards created by Motorola SRS and ColdFire design teamMotorolaTempe, AZ 19951998Embedded SoC Design EngineerTechnical lead and project manager of imaging and storage SoC project developed for Iomega Jazz product delivered on-time and production ready 1st silicon met performance/cost/business goalsSuccessful design and integration of a configurable serial interface module which serviced a range of customer protocols and requirementsMotorolaTempe, AZ 19911995MC68060 Design Verification EngineerDesign architect of MC68060 microprocessor verification platform implemented in Verilog to provide the simulation infrastructure during 060 MPU development, then rapid prototyped into FPGA, and ultimately placed/routed into a high-performance PCB implementation used for silicon evaluation/debugEdge ComputerScottsdale, AZ 19851991Senior CPU Technician/Engineering AidWorked closely with CPU architects to create successful verification methodologies for proprietary CPU micro-mainframe (binary compatible 68K ISA)EducationDeVry Institute of Technology Phoenix, AZBachelors Degree in Technical Management 19951997DeVry Institute of Technology Phoenix, AZAssociates Degree in Electronics Engineering 19821984Core CompetenciesRTL Design, VHDL, SystemVerilog, Testbench Design, High-Speed SerDes Equalization Algorithms, CPU, DDR Microarchitectures, Lua, Python, Perl, C/C++ Firmware, ARM, X86, 68K, PowerPC and ISAs, mixed signal, Matlab, coverage tools, assertions, LEC, ATPG, Primetime/Tempus STA, DFT, multiple clock domains, power/clock gating, low-power UPF, Linux, PCB design/layout/route, FPGA, GLS/SDF, performance modeling, Visio, MS-Office, FrameMaker |
