| Candidate Information | | Title | Application Engineer Validation | | Target Location | US-OR-Hillsboro | | Email | Available with paid plan |
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Click here or scroll down to respond to this candidateDai HoHillsboro, Oregon Street Address (503)703-6805 EMAIL AVAILABLE https://LINKEDIN LINK AVAILABLE APPLICATION/TEST/VALIDATION ENGINEERIntel Silicon Application Engineer. Support Silicon Full Cycles (ASIC Development Silicon Validation PCB Design-In System Power On Test Debug Launch High-volume Productions). Collaborate across multiple teams (designer, hardware, software, marketing, mechanical, manufacture, etc.) for debugging issues as they arise. Own data collection, failure analysis, collateral developer, application note, and technical validation report. Looking for next challenge as an Application Engineer, Test/Validation Engineer, or Electrical Engineer. US Citizen. Bilingual in English and Vietnamese. Travel Street Address %. On-site/Hybrid. TECHNICAL SKILLIntel IEEEStreet Address .3 Ethernet Base-T Expert PCB Reference Design Customer Design Review Power-On Activities OEM/ODM Customer Support ESD, EMI Silicon Power Delivery Test Plan Development Failure/Data AnalysisIssue Debugger Power Measurement/Performance Power Noise Analysis Validation Report PCB Board Design Tools Oscilloscopes, Power Supplies, Electronic Loads, Signal Generators, VNA, etc. Laptop 6-cell Battery Power Validation Silicon/System Performance 23 Year of Experience working on Consumer Electronics EXPERIENCEIntel Corporation (Hillsboro, Oregon) total 23 years of experience June 2000 October 2023 ASIC Application Engineer April 2021 October 2023 FAE for Intel Blockscale Bonanza Silicon. Successfully supported launching Bonanza silicon to market on-time. Supported Intel Blockscale ASIC (bitcoin cryptocurrency mining). Provided demo to Intel Customers. Tested High-Power Stress Conditions. System Power Consumptions. Developed Datasheet and Design Guide. Developed Test Procedures for Technicians to follow. Automated System Test. Debugging and Troubleshooting issues. Electrical and Function Tests. Evaluated the Immersion Cooling Solution for Bitcoin Miner Unit. Hardware Lab Manager (2 Technicians). Network Hardware Engineer January 2006 April 2021 15 years long journey as a key FAE hardware-related engineer for supporting Intel Ethernet Base-T I219/I225/I226 silicon products. Technical support for multi-million silicon in mass productions. IEEE802.3 Ethernet Standard Expert. Analog front-end, magnetics, ESD protection. Python Automation. Designed and Validated Power Solutions for LAN applications. Ethernet Battery Power Impact study. Silicon Collaterals: Reviewed Technical Docs. Owned Datasheet and Schematic/Layout Design Guides. Platform Designer & Validation June 2000 January 2006 Designed/Calculated Power Distribution for Intel Concept-PC. Supported Intel Corporate CES/IDF Demo. Calculated System Power Delivery. Designed LVR/SVR Power Solutions. Supported Power-on Activity. Electrical Signal Measurements. Power Performance Analysis. BOM & Component Evaluations. I2C, SMBUS, Signal Integrity, Power Measurement, Data Collection, Failure Analysis, Issue Debugger. Electrical/Functional Validation on Battery vs AC Power Supply. Mechanical/Thermal/ESD/EMI/etc. EDUCATION/OTHERMaster of Science: Electrical Engineering. Oregon Graduate Institution (OGI/OHSU, Portland - OR) Bachelor of Science: Computer Engineering. Portland State University (PSU, Portland OR) Engineering Level: Intel Engineering Level-7 (Senior). x3 Promotions. x3 Division Awards. Reference: Most Recent Manager. Ram Rajagopal, (916)202-9839. https://LINKEDIN LINK AVAILABLE |
