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Click here or scroll down to respond to this candidate Design / Test / Application Engineer An innovative professional leveraging extensive experience in product design and development, hardware/firmware/software expertise, and project management to propel next-generation technologies to market.Top-Line Contributor: Leading development and expansion to seize emergingand untapped marketsGrew IBM's Digital Video Products group from 0 to over $50M annual revenue,originating technical offerings.Generated $5M annual sales by co-developing a built-in self test solutionfor general logic and embedded memories; designed hardware and softwaresupport scripts; marketed services to prospective clients.Innovative thinker, creating 11 patents, including one recognized as a top10% royalty earner for IBM.Product Expert: Elevating net worth by upgrading legacy offerings androlling out new servicesPioneer at-speed test methodology for next-generation IBM semiconductortechnology, improving chip quality.Integrated high worth functions to expand product line, including PowerPCprocessor, audio decoder, and high speed serial IP (USB, DDRx, HBM) tocreate complete single-chip solutions.Designed motion compensation unit to drive a ground-breaking single-chipMPEG-2 video decoder launch.Collaboration Specialist: Building internal and external relationships inmultinational environmentsImprove overall customer satisfaction 10%+, reducing open-ticket max timefrom 180 days to less than 60 days.Achieved superior ratings on customer care benchmarks measuring resolutionquality, quantity, and timeliness.Partnered with development, verification, support experts, manufacturingengineers, and customers in the Americas, Europe, Australia, and Asia. Technical Proficiency Digital Design ? Architecture ? Hardware Integration ? Logic Synthesis ? RTL & Gate Level Simulation Timing Analysis ? ASIC/FPGA ? Formal Verification ? Design-for-Test ? IP Core Macro Test IEEE 1687 ? IEEE 1149 ? LBIST & MBIST ? Hardware Bring-up & Debug ? System Validation VHDL/Verilog Design Languages ? Product & Customer Support ? FrameMaker ? UNIX/LINUX ? MS Windows/Office tools ? Team Communication ? Engineering Analysis Team Leadership ? Technical Documentation ? Project Management Professional OverviewSenior Staff Engineer . Marvell Government Solutions - Aug. 2021 -May 2023Subsidiary of Marvell Semiconductor, focused on delivering custom ASICsolutions to the Aerospace and Defense (A&D) industries.Integrate IP cores into ASIC chip-level methodology by incorporatingadditional test structures/wrappers and proving rule functionality throughthe entire front-end process/methodology by integrating a test part usingthe IP.Synthesize IP RTL (Synopsys DC) and resolve all timing issues working withdesign team, to fine tune assertions and correct design issues.Insert scan/DFT structures using standard ASIC methodology procedures.Verify results at each step using formal verification tools (Synopsys /Cadence) to prove functional equivalence between RTL and tech-mappednetlistCreate verilog test patterns (Cadence-Modus) and verify function againstrelease gate-level verilog netlist using NCSim & SimVision simulationtools.Coordinate with manufacturing test engineers to validate hardware andoptimize tests on production hardware.Create portable manufacturing test cases using IEEE 1687 ICL and PDL formatto verify the analog functions, again using gate-level simulation tools.Clean Room Technician . Rheonix - Ithaca, NY Oct. 2020 - Jun. 2021Privately held company providing fully automated and integrated molecularbiologic testing devices .Collaborating with manufacturing engineers and automation consultants, setup multi-module automated production line, isolate and resolve operationalissues to bring line into full production mode.Act as primary contact to resolve problems with automated card line,laminators, laser cutters, and other machines reported by operators.Investigate problems to discover root cause, implement mechanical,electrical, PLC fixes to return machines to operational status.Learn and perform various clean room operating procedures to buildproduction parts for increased volume supporting FDA Emergency UseAuthorization while maintaining quality targets.DFT Engineer . Global Foundries/Avera Semi - Endicott, NY Aug. 2016 -Jan. 2020Global semiconductor foundry providing advanced technologies and ASICsolutions.Analyze and process leading edge IP cores and generate test rules forrelease into ASIC design libraries/design kits, ensuring GF's technicalportfolio leadership.Interface closely with world-wide teams, ensuring core designs meettestability standards using Cadence Modus (clock domains, scanimplementation, X-source, coverage) for both digital and analog functionaltests, driving issues to resolution.Drive designs through chip integration methodology to ensure smoothworkflow, interfacing with methodology and design automation teams toresolve issues prior to release of design kits.Using guidance from IP development teams, create functional test patternsfor manufacturing test of analog circuitry of the cores (IEEE 1687 ICL/PDLand Cadence Modus). Verify patterns through verilog netlist/gate-levelsimulation and finally with manufacturing test engineers to debug/optimizeon early hardware.Analyze/debug ATPG patterns through simulations (Cadence NCSim & SimVision)on gate-level netlist models, following-up with manufacturing engineeringto ensure proper operation on actual hardware. Analyze expected/actualvariances to determine root cause and correct.Minimize production costs through close involvement with manufacturing testgroups to ensure specification compliance, quality, performance, andmanufacturing yield are maintained.DFT Engineer . SiliconAid Solutions - Austin, TX June 2011 - July2016Privately held company specializing in design-for-test solutions fordomestic clients.Contract consultant to IBM and Global Foundries supporting ASIC serial linkcore development, providing portable test solutions for core IP incollaboration with internal technology groups and third party vendors todrive innovation and integration of new technologies.Verify gate-level verilog netlist based model against test tool guidelinesfor scan structures; clock control and gating, domain crossing; testcoverage; x-source gating; BIST structures; IEEE 1149 & 1687 compliance;etc..Build test tool (Cadence Encounter Test/Modus) based test model rules andrelated files/rules and promote into technology libraries/design kits forrelease to customers.Simulate ATPG patterns from test model against gate-level hardware modelto verify correct ness.Assist ASIC chip design teams with integration of cores to ensure first-time-correct chip designs.Generate and verify manufacturing test patterns targeting analog and/or non-ATPG logic to ensure manufacturing and product quality targets are met orexceeded.Contract Consultant to Cadence developing At-Speed Structural Test andLBIST initiatives for Modus product.Hardware Applications Engineer . Advanced Design Consulting - Lansing,NY Aug. - Nov. 2010Privately held company with global reach specializing in unique high-precision apparatus for research and academic clients.Consultant contracted to 'jump-start' a time critical project to fulfillgovernment contract requirements and guarantee continued funding.Gain working understanding of Microchip Technology's processors (PIC24MPU), peripherals, debug tools and application software.Debug and update existing hardware/firmware design using MPLAB/PICkit toolsto ensure proper communication between processor and RF transceiver module.Provide hardware/firmware resolutions to technical issues with embeddedsystem and get project back on schedule within three month operationalwindow.Field Operations Supervisor . US Census Bureau - Elmira, NY Feb. - Aug.2010United States Department of Commerce - Decennial Census Operations.Train, deploy and manage a field force of 100 people across a three countyregion in upstate New York.Develop high functioning management and employee team in a very short timeframe to accomplish field operation goals.Manage logistics, personnel, and public relations aspects for a highlyvisible government operation.Senior Consultant . Cadence Design Systems - Endicott, NY Nov. 2002 -Nov. 2008Global provider of electronic design automation software and designservices generating $1B+ annual revenue.Primary support consultant for lead customer account, overseeing high-endprocessor development groups, building strong relationships and increasingcustomer satisfaction measures to maintain significant funding stream.Respond to incoming customer problem reports, working with them tounderstand the issue and gather testcase information. Study the problem tounderstand the root cause, determining whether it was a usage issue,customer design issue, or an actual tool problem.Follow up with customer on usage/design issues to resolve, or with internaldevelopment team to create a fix/functional enhancement for tool issues.Verify any fixes against customer testcases and regression suite to ensureoverall tool quality. Closely track issue status to ensure timelyresolutions and maintain a high level of customer satisfaction.Develop, market, and support automated built-in self test solutions forlogic and embedded memories, building a new revenue sourceUnderstand customer plans for new methodologies and match that againstexisting capabilities in Encounter Test, map out enhancements as requiredfor new development efforts, track and verify updated functionality.Coordinate with teams spread across Europe, Asia, and the US, providingbest-in-class product solutions.Advisory Engineer/Lead Designer/Product Engineer . IBM Corporation -Endicott, NY prior to Nov. 2002Instrumental in growing IBM digital video products group from start-up intoa $50M entity. as part of a 20 member team to actualize research intoproduct development.Interpret specs to create high-level/low-level designs, RTL implementation,functional simulation, and synthesize to target ASIC/FPGA technology tomeet timing, power, and floor-planning size constraints.Directed ten designers as decoder Team Lead, supervising project planning,workload, and schedules.Guided total life-cycle development in product engineer and lead designpositions; product lines included MPEG video, 9221 four-way channel-to-channel control units, and S/390 and S/370 processors.Developed microprocessor-based subsystem and diagnostic software to detecthardware problems and engineered resolutions with field teams.Performed architecture definition, hardware and software analysis, digitaldesign, simulations, verification, timing closure, debug activities,customer service, and maintenance support on multiple products. Academic Credentials Master of Science, Computer Engineering: Syracuse University Bachelor of Science, Electrical Engineering: State University of New York at Buffalo Patents & Publications 5 Papers Published 11 US Patents Certifications and Affiliations New York State Intern Engineer, certificate #028056 Member of IEEE, Binghamton section United States Citizen |
