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Click here or scroll down to respond to this candidateCandidate's Name , Ph.D.Austin, TexasPHONE NUMBER AVAILABLEEMAIL AVAILABLESUMMARY OF QUALIFICATIONS Accomplished Performance Architect with expertise in processor and system performance modeling and analysis using in-house and EDA vendor tools. Adept at leveraging program management and project management skills to drive hardware and software development. Recognized for the ability to optimize system performance. Demonstrated technical management and leading people. Skilled at mentoring, coaching, hiring and building teams. Areas of competence include Design trade-off analysis and performance projection of CPUs, caches, DDRs, interconnects, hardware accelerators, and SoCs. Programming skills in C, C++, System C/ TLM 2.0, and object-oriented design. Power estimate at the beginning of design cycle using performance simulation models. Memory bandwidth optimization that can be used for GPU performance analysis. Software application workload characterization and benchmarking Teaching college-level computer science courses. Work well with vendors and diversified customers. Professional ExperienceAdvanced Micro Devices Austin, Texas 6/21/2022 11/30/2023 Power and Performance Attainment Lead (PPAL) Power and performance analysis of CPU, GPU and SoC products. Working with analytical and simulation models for power and performance projection. Correlation between measured silicon numbers against projections of various metrics. Performance analysis of AI, ML, DP and other customer workloads traces IBM Corporation Austin, Texas 2019-2022Chief Performance Architect System modeling team lead Leading a team of several performance engineers to develop system performance models, validate them, project performance, do bottleneck analysis, and suggestion to improve design for better performance improvement. Trace analysis to find workload sensitivities to performance Using both simulation and analytical models to project performance Our focus is mostly on enterprise workload for system performance analysis Looking at the best methodologies for current and next generation CPU and SoC architecture performance modeling and analysis. That includes model development, workload characterization and analysis methods.NXP Automotive Austin, Texas 2017 2019Sr. Performance Verification Lead Developed micro-benchmarks and other performance tests to verify the performance of automobile SoCs. Studied the micro-architecture documents, developed data flows for different applications, defined various data flow parameters, developed micro-benchmarks and ran them on the RTL verification test benches and other performance models. Studied the SoC bottlenecks by developing the relevant performance tests and ran them on the SoC simulation models. Educated the performance verification teams with performance architecture, performance verification and bottleneck analysis.ENCORE SEMI Austin, Texas 2016 2017Senior Performance Architecture ConsultantAssisting Encore Semi with System Performance Modeling (SPM) services INTEL CORPORATION/LSI LOGIC Austin, Texas 20142018 Atom CPU Lead Performance Architect and Manager (2014-2016) Spearheaded development of CPU and SoC performance models after LSI purchase by Intel and deliveredthem to external customers. Led a team of 10-12 Hardware Engineers. Managed and actively participated in the CPU model development using C++, architecture exploration, architecture validation, pre and post silicon power and performance analysis, SoC teams support, workload characterization and tracing. Helped secure ~$100M design win by working closely with the internal and external customers and vendors to understand technical requirements and communicate them with the team. Improved company-wide performance modeling and validation methodology by actively participated in various work groups.LSI Corporation Austin, Texas 2008 - 2014Distinguished Engineer and Modeling Lead (2008-2014) Individual contributor and team lead in developing system performance models in C/C++, SystemC/TLM 2.0, and Synopsys Platform Architect for performance analysis of SoC products. The models include ARM processor cores, ARM coherent interconnects, dedicated hardware engines, I/O devices, buses, caches and memory controllers. Key contributor to design wins by enabling customers to estimate their in house application performance. Developed methodology for modeling and analysis of customer applications before software simulators became available. Improved LSI competitive position by analyzing performance of standard benchmarks such as Dhrystone, Lm Bench, EEMBC, and customer specific customized benchmarks. Determined and resolved bottleneck of a baseband processor chip by using Synopsys Platform Architect. Improved memory bandwidth by using carbonized memory controllers in the SoC performance model.FREESCALE SEMICONDUCTOR Austin, Texas 2004 - 2008 Senior Member Technical StaffIndividual contributor and team lead to support architecture performance analysis of PowerQUICC and P4080 SoC products. Used in-house C++ and SystemC based modeling tools to analyze performance of SoC systems. Detected and resolved serious bottlenecks before tape-out by developing transaction level models for architecture and application models. The SoC models included processor cores, caches, busses, DDR2 and DDR3 memory subsystems, Ethernet, Quick Engines, PCI, security devices, pattern matching engines, arbiters and bridges.AGERE SYSTEMS (formerly LUCENT) Austin, Texas 2000 2004 Distinguished Member Technical Staff/Technical Manager Individual contributor and leader of team of engineers to support architecture and design of 10 Giga bits per second network processors, traffic managers, and switch fabrics through performance engineering. Supported marketing, hardware and software teams with performance analysis and benchmarking of network processor products. Developed performance simulators in C/C++ and Java for network processors, traffic managers, and switch fabrics. Represented Agere Systems for benchmarking at Network Processor Forum for three years. Chaired benchmarking task group at NPF for three years. ADVANCED MICRO DEVICES Austin, Texas, 1995-2000Senior Member Technical Staff System Performance Modeling Technical Manager IBM CORPORATION - Austin, Texas. 1987-1995Advisory Engineer PowerPC CPU Performance Modeling Technical Lead Motorola Corporation - Austin Texas, 1984-1987EDUCATIONPh.D. in Electrical and Computer Engineering, The University of Texas at Austin MS in Electrical and Computer Engineering, The University of Texas at Austin ADDENDUMPUBLICATIONS Candidate's Name , D. N. Jayasimha, Multicore SoC Performance Modeling and Analysis, ARM Technology Conference, October 2013. Candidate's Name , Experience from the Field, Building SoC Architecture Performance Models using In-house and 3rd Party IPs, Design Conference, SystemC User Group, June 2013. Candidate's Name , Anthony Fama, SoC Architecture/Performance Modeling using SystemC/ TLM-2.0, a Case Study using Synopsys Platform Architect, Synopsys User Group (SNUG) Conference, 2012. Candidate's Name , A Common System Memory Model for SoC Software and Architecture Models using a SystemC/TLM-2.0 interface, DVCON SystemC User Group, February 2011 Candidate's Name , Performance Analysis of Multi-core SoC Systems, Embedded System Conference, April 2004. Candidate's Name , Benchmarks Rates Switch Fabric Performance, Computer Design, December 2003 Candidate's Name , David Christie, Generation of 3D Graphics Workload for System Memory Analysis, IEEE Micro 31, workshop on workload characterization, November 1998. Candidate's Name , System Performance Modeling and Analysis, International Symposium in Computer Architecture, workshop on system performance analysis, Barcelona, Spain, June 1998 Candidate's Name , Performance Analysis of Super-Scalar Microprocessors , Invited speaker at the Conference on Computer Applications in Industry, Taiwan, February 1996 Candidate's Name , et al, Characterization of Performance projection Accuracy in Trace Driven Simulation Environment, IBM Technical Report, APR, 1995 Candidate's Name , Chuan L. Wu, " Trace Sampling for Design Trade-off of Microprocessors Using SPEC92 Benchmarks", Proceedings of IEEE IPCCC, pp. 87-94, March 1995 Candidate's Name , " The PowerPC Performance Modeling Methodology", Communication of the ACM, June 1994, pp. 47-54 Candidate's Name , et al, "The PowerPC 603 Performance Analysis and Design Trade-off", Proceedings of IEEE COMPCON, pp. 316-323, Feb. 1994 PatentsAwarded five patents and numerous invention disclosures in the area of microprocessor design and high- speed traffic management.PersonalMarried and a US Citizen |
