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Click here or scroll down to respond to this candidateCandidate's Name
Street Address MT Baker Place N.E Phone: PHONE NUMBER AVAILABLERenton, WA. Street Address Email: EMAIL AVAILABLEOBJECTIVE: Looking to obtain a job as an experienced IC Circuit of Electrical Engineer position to modify existing layouts and utilize my knowledge in the IC design by performing layout cells in analog, digital, mix signal and top level layout.SKILLS PROFILEOver seven years of experience in working with Cadence layout toolsetFamiliar in working with Unix, Cadence Virtuoso XL, Diva (DRC/LVS/ERC), (DRC/LVS) and Hercules Avant (DRC/LVS/ERC/ANT), and Assura verification toolsKnow how to modify existing layouts, DRC, LVS, and arrange layout cellsExperience with design digital standard cells, analog layout, guard ring and full chipEMPLOYMENT HISTORYAviation Maintenance Technician, Allflight Corporation, Kent, WA 07/05/2022-currentAssist lead technicians with cleaning, prepping, inspecting, testing and repairing aircraft windows, components and equipment.Production Assembler, Hy Security, Kent, WA 02/28/2022-06/21/2022Assemble electric box, panels of gate security system with batteries, transformer, chassis, wire harness routing.Test Technician, Sanmina, Bothell, WA 03/15/2021-11/04/2021Perform defect finding on circuit boards, repair and replace electro-mechanical componentsRead schematics, diagrams from eMatrix. Measure resistors, capacitors, impedance. Check for voltage short and open components on circuit boards.Perform functional imaging testing of a finished medical ultrasound device.Perform resilient self-test, calibration for channel board and transducer select board on space station.Record each component replaced in Elog for company and Rep Track for customers.Mechanical Assembler, Fluke, Everett, WA 09/28/2020-02/17/2021Visual inspect, assemble face masksMeasure, cut pipes and boards; assemble shelves under worktables.Assemble magnetic sliding tool kits and chain with keys for alignment sensors, solder batteries wires to PCB boards for rotalign sensor and solder batteries wires through holes for optalign sensor. Wrap electrical wires under batteries with insulation tapes around batteries. Assemble some packages for laser light: rotalign and optalign. Labels and packages for Thermometers, Digital Multimeters and Clamp MetersTest RH percentage of Relative Humidity and Temperature Meters at 75 percent RH with salt and distilled water. Report pass/fail data.Mechanical Assembler, Aim Aerospace, Auburn, Washington 11/20/2017-07/02/2020Install sleeve and insulation for aircraft ductingPrepare panels, cleaning with alcohol, read documentsPrepare bonding mixturePerform etching process for panels with bonding mixtureInspect panels and fix minor etching detailsMechanical Assembler, BTG, Bothell, Washington 11/21/2012-8/13/2015Work in clean roomSolder elements to core wires under microscopeAssemble core wires with elements that can go into blood veinsIC Layout Engineer, TriQuint, High Point, North Carolina 5/2012-5/2012Worked with layout of 3 metal layers of VLSI RF layouts for updated diode, clamp, and esd pads in IBM_PDK RunsetModified existing layout and debug problem in the LVS data report for substrate floatingLayout tools: Cadence Virtourso and IBM_PDK with DRC and LVSMechanical Assembler, Eldec,Corporation, Lynwood, Washington 11/2011-03/2012Calibrate test machineAssemble inductors coilsTint wiresSolder wires between inductor coils under microscopeCalibrate inductors within specified frequency rangeTint conductorsWrap inductor wires to conductor wiresTouch up solder.Analog Layout/Mask Engineer, Impinj, Seattle, Washington 11/2010-12/2010Modified existing layouts of a VLSI RFIC memory in 45nm techngoloy.Design layouts for controlling circuit section that in charge of memory tags: aeon_bias and aeon_bias vittoz.Worked with layout tools: Cadence Virtourso/Virtourso XL and DRC/LVS/ANT/ERC Assura verificationAnalog Layout/Mask Engineer, Zarlink, San Diego, California 07/2009-10/2009Worked with floor planning and VLSI layouts of a hearing aid in 18nm tsmc RF technologyDesign layouts of 4 esd-pads and 1M-ohm resistorDesign layouts for an oscillator and charge pump in CM018MMRF technologyDesign connection of m3 between the hybrid layout and decoders layoutDesign layouts for switches and caps for a decimatorWorked with layout tools: Cadence Virtourso/Virtourso XL and DRC/LVS/ANT/ERC Assura verificationMechanical Assembler, Carlye Inc, Tukwilla, Washington 01/2006-07/2007Work in a teamStrip wiresCrimp pinsHeat shrinkAssemble cablesAnalog Layout/Mask Engineer, Semtech, Mira Mesa, California 10/2005-10/2005Worked with floor planning of a VLSI arrayModified existing layouts and fixed DRC errors from a gds file: dac16 layout in Bipolar and 35nm polar technologyModified existing layout for schematics with bipolar transistors and analog devices, pcomp and pcomp0Modified existing layouts for three stages of a comparator: plogic, plogicd and plogicoModified existing layout for a schematic, imirror9 with npn and pnpWork with layout tools: Cadence Virtourso/Virtourso XL and DRC/LVS/ANT/ERC verification with Hercules Avant!Physical Design Engineer, Intel, Hillsboro, Oregon 11/2003-12/2003Design VLSI layouts of logic control in 80 nanometer CMOS technologyWork with digital layout block. Design layouts for nvstctl_jtagtop with padin and padout. Draw layouts for nvstctl_jtagselaccess5, nvstctl_jtagmux4, jtagselaccess5, nvstctl_jtagtrxmux, nvstctl_jtagdomux, txrmux, tdmux, nvstctl_jtagtdomux, nvstctl_seldecoder, decap, pad in/pad out, buffers and nvst_ctl_jtagtop control blockModified exixting high-speed layouts of phase locked loop, logic divider, flip-flop and charge pumps for a high-speed and low power addressableWork with layout tools: Cadence Virtourso/Virtourso XL and DRC/LVS/ANT/ERC verification with Hercules Avant!Physical Design Engineer, Intel, Hillsboro, Oregon 10/2002-1/2003Design layouts for VLSI p861 chipset projectWork with pipeline architectures, rows and columns for a chipset. Design data path in patterns that feed data from right to left and from top to bottom for multiple rows/columnDesign I/O connections in different layout structuresModified existing high-speed layouts for dataspinebufblk, basebufblk, globalbufblk, compfiller, leftspinebufblk, leftsplinevss and clkgenFixed shorts and overlaps in layouts with power template. Fix lvs errors in layouts of front-side busesDesign decaps for VDD pad and VSS pad to reduce power noiseDesign layout for high voltage decaps layout with VCCDDR and VSSTroubleshoot LVS errorsAlign metals, m6, m4, m5 and m3 to reduce inductances in layout of top_comp.Worked in ddr_anaprdrvr layout to connect between multiple power rails and padConnected vcca to vcc, vssa to vss, vccddr to vccddr, and esd to pad in a top level layoutFix text labels in top-level layout and input padsPerform all verification flowsWork with layout tools: Cadence Virtourso/Virtourso XL and DRC/LVS/ANT/ERC verification with Hercules Avant!Analog Layout Engineer, CMOS Micro Device, Campbell, California 3/2002-3/2002Design layouts for memory chip projectWorked with layouts of phase locked loop (PLL), logic divider, Op-amps, flip-flop with bi-directional transistors, and charge pumps in 18nm TSMC technologyWork with layout tools: Cadence Virtuorso/Virtourso XL, DRC/ERC with Diva, and LVS with DraculaAnalog Layout Engineer, NSC, Santa Clara, California 10/2001-2/2002Worked with floor planning of existing VLSI layouts for audio chipsModified existing layouts of op-amps, resistor chains, volume controller, selectors for lm4841 chip projectDesign layouts for capacitors with common centroid among themWork with floor planning and single/double guard rings in cs65sg high voltage technologyFixed LVS errors for lm4842chipModified existing layouts for lm4901 chip in cs7_5v technologyModified layouts for lm4890 projectDesign pad ring to cover substrate area for lm4894 layout chipWork with layout tools: Virtuoso-XL with P-cells and DRC and LVS with Diva for small audio chipsAnalog Layout Engineer, IC Media, Mesa, Arizona 1/2001-7/2001Design layouts for project 108tWorked with pad rings for VLSI project 532 layout and I/O connections for 105_V2Fixed layout errors of an ESD layout pad with a tri-state bufferTested a DRC deck in 0.25micron UMC technology.Worked with data paths and arrays for project 108t CMOS Imager PC CameraWorked with layouts of ramp generator, ADC, voltage generators and PLL8001Design layouts for row decoder, column decoder, clock control logic, comparatorWorked with floor planning of a 1290x1034 CMOS imagerDesign data paths of 1290x1034 CMOS pixels imager with 4.5um pitch with 45nm UMC technologiesAssigned pin locations in layout for analog/digital, and provided a double power source for the imagerWork with layout tool Cadence Virtuoso; DRC/LVS/ERC/ANT with Diva and HerculesAnalog Layout Engineer, Global Span, Princeton, New Jersey 7/2000-7/2000Worked with inputs of interconnection of transistors in arrayApplied matching technique for transistorWork with layout tools: Cadence VirtuosoCompiler/Verification Engineer, Virrage Logic, Bellevue, Washington 1/2000-2/2000Draw VLSI layouts for I/O of dual CMOS RAM memoryVerified the dual CMOS RAM architecture and documentsWork with layout tools: Cadence VirtuosoTechnical Co-Op student, JPL, Pasadena, California 3/1998-10/1999Design rule check and fix width and length of layout transistors.Design rule check and work with spacing between metals and poly layersVerify layouts of a twelve bits Sigma-Delta ADC of a video camera.Design schematics for a 12 bit adder and Op-Amp at high gainModified existing ADC layout from MOSIS technology to Lockheed Martin technologyRecord test chipsWork with layout tools like L-Edit and CadenceTechnical Co-Op student, JPL, Pasadena, California 6/1997-12/1997Draw I/O connection for data path between four special purpose chipsBuild test boards on breadboardWork with Labview to assist an engineer in a moving robot.Assisted other technical staff in circuit simulationDesign layout of a VLSI 4:1 split array transistorsRecorded data of some simple test chips from oscilloscopeWork with software tools: OrCAD and MicroSimEDUCATIONBachelor of Science in Electrical Engineering 1998University of Washington, Seattle, WA |
