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Click here or scroll down to respond to this candidate ANOOP KU MAR
Street Address Cedar Bend Dr. A ustin , TX PHONE NUMBER AVAILABLE EMAIL AVAILABLE
SU M MARY O F Q UAL I F I CAT I ONS
Dedicated and resourceful professional with 14 years experience in optimizing code generation and compiler
construction, primarily on the sun-sparc C++ production platforms and a variety of phases of optimizing code
generation. Exceptional background in areas of data structures, algorithms, retargetable code generation, instruction
scheduling, register allocation and software pipelining. Analytical and creative individual with a proven record of
developing innovative solutions to complex problems and excelling in high-pressure situations. Proven ability to
master cutting edge technology and integration into company framework by applying foresight and strategic planning
skills.
V ALUE O F F E RED
Optimization - Strong understanding of Attention to Detail - Resolved critical customer
optimization and code generation techniques for bugs in 1-2 business days or provided work around
d ifferent versions of sparc architectures, Fujitsu, Sun after root cause was identified and extensive testing
M AJC (VLIW architecture), ARMv7-M Cortex was completed.
p rocessor, Motorola DSP chip (VLIW architecture)
and S3 DSP architecture. Design and Development - I mplemented
support for VIS 3.0 instructions in the SPARC Code
Performance Tuning E nhanced Generator part of Oracle Solaris Studio. VIS is Sun's
performance of application like Oracle, SAP and extensions to the Sparc V8/v9 ISA to aid multimedia type
applications. Integrated register allocation and
benchmark like spec2000, spec2006,coremark.
i nstruction scheduling, vectorization and software
Volunteered for on-site application tuning at
p ipelining.
I nformatica and achieved 28% performance
i mprovement.
SK I L LS T OOLS E XPER I E NCE
A ND
P rogramming Languages: C++, including STL, Perl, Unix shell script
Operating Systems: Solaris, AIX, Linux, Windows
Tools: Lex, Yaac, Eclipse, Performance Analyzer for data application, gdb, dbx, purify, gprof, Clear Case, cvs
P ROFESSIONAL E XPER I E NCE
I B M I NNOVATION CENTER. - A ustin, TX Since
J une 2012
Senior Software Consultant
Working on LVM(Logical Volume Manager) in AIX kernel.
Resolved time sensitive issues in LVM within couple of hours. In most cases customer faced system
shutdown.
Implemented branch and bound solver for PBQP(Partitioned Boolean Quadratic Programming) graph in
register allocator in LLVM in C++ on Linux, and did comparative analysis with existing register allocator in LLVM.
ANOOP KU MAR
Page 2 of 2
F REESCALE SEM ICONDUCTOR - A ustin, TX J une
2010 to Jan 2012
Senior Complier Engineer Level 4
Responsible for the mentoring over oversees team.
Involved in the design and implementation of machine independent optimizations in IR, resulting in 5%
performance improvement in coremark benchmark.
Designed and implemented algorithm to handle unaligned branch target for mix of ARM, Thumb and
T humb2 instructions mix.
Collaborated on CW compiler backend peep hole optimizations for ARMv7-M cortex for coremark
benchmark.
Analyzed the root cause of regressions in several EEMBC benchmark.
I NTELL IQUESTTEK , L LC . - Self Employed, Mountain View, CA Jan
2009 to July 2010
Consulting
Endeavored in commercializing University research in compiler
Mentoring and consulting in Linux.
SUN M ICROSYSTEMS I NC. - Menlo Park, CA
1999 to 2008
Senior Software Engineer
Language: C++
Operating System: Solaris
Division: SPARC Compilation Technology Group-Code generation team and Postoptimizer (2002 - 2008)
Designed and implemented prototype integrating register allocation and instruction scheduling for Post
Optimizer (US Patent 7007271).
Designed and developed retargetable machine model generator for detecting structural hazard for
i nstruction scheduling in Postoptimizer.
Created prototype for vectorization for SIMD support for SPARC architecture.
Implemented inlined version for library function strcmp, strncmp, strcasecmp, strncasecmp, memcpy
memset, memcmp, memmov, sqrt, fabs.
Provided structure copy using VIS instructions and evaluated performance improvement over the one
w ithout using VIS instructions.
Shared responsibility of code reviewer and bug evaluator with team members in rotation.
Interacted with processors architects for future generation of Sparc family, throughput computing
a rchitecture and Fujitsu chip.
Added ISA changes support for new features for architectures in code generation instruction selection phase
and assembler.
Studied to make code generator source code multithreaded so routines in program can be optimized as
i ndependent thread in parallel.
ANOOP KU MAR
Page 3 of 2
Involved in sgcc4.2 (sparc gcc) release and added support for gnu style asm statement in sgcc4.2.
Solely responsible for assembler and disassembler which was shipped with Solaris.
Owned yabe (fast code generator), compile time improvement by 32% on spec2000 in fast code
generator.
Vital part of the implementation of c/c++/java/fortran languages in code generation
Improved performance 28% by changing source code and compiler f lags by working on-site tuning
application at Informatica.
Performance tuning for commercial application, spec 2000, and spec 2006.
Division: MAJC Compiler (1999 - 2002)
Responsible for the design and development of features and optimizations in the MAJC compiler (VLIW
a rchitecture targeted at Multimedia and graphics) using gcc-2.8 front-end.
Designed and implemented Slack scheduling which replaced gcc basic block list scheduler resulting in 150%
performance improvement on media benchmark.
Performed Peephole optimization for improving the performance for MAJC specific architecture
optimization for sign extensions, SIMD related code for MAJC.
Implemented a variety of optimizations in gcc combiner phase, which exploits ISA features to combine the
related operations.
Changed parts of the gcc front-end to simplify MAJC specific optimizations.
AD D I T I O NAL WORK EXPER I E NCE
Spike Technology (Qualcomm) , M ilpitas, CA - Consultant Engineer
1998 - 1999
Motorola I ndia Limited Software Engineer
1998
S3 Limited. Software Engineer
1997 - 1998
E D UCAT IO N H ONORS
A ND
I ndian I nstitute of Science - Bangalore, India
1997
Master of Engineering In Computer Science and Engineering
US Patent 7007271 - Method and Apparatus For Integrated Instruction Scheduling and Register allocation in
postoptimizer.
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