Title: NPU (Neural Processing Unit) Architect Location: Santa Clara, CA (Onsite) Duration: Full-Time Salary: $250K + 10% Bonus + Equity The NPU (Neural Processing Unit) Architect will be responsible for designing and optimizing NPU architectures to improve performance, power, area, and flexibility for various neural networks in our series chips. This role will require analyzing existing and emerging neural networks to identify bottlenecks and areas for innovation and applying innovative approaches to design and optimize NPUs. The ideal candidate should have experience in NPU micro-architecture, RTL, simulator, and compiler to refine and assess the feasibility of ideas. Responsibilities Define new NPU architectures and optimize existing ones to improve performance/power/area metric and flexibility for neural networks. Analyze existing and new emerging neural networks to identify bottlenecks and opportunities for innovation. Use innovative approaches to improve NPU architecture. Possess experience in NPU micro-architecture, RTL, simulator, and compiler. Assess feasibility of ideas and refine them. Qualifications 5+ years of experience in hardware design projects in architectural or micro-architectural level. Experience in PPA (power/performance/area) optimizations. Familiar with hardware description languages - SystemVerilog. Programming skills in C/C++. Preferred qualifications Experience in NPU, GPU, and micro-processor development; especially many-core and multi-chip systems. Experience with ML frameworks (Tensorflow, PyTorch, TVM, and so on Experience in architecture exploration tool development. Experience in hardware simulator development. Experience in compiler development. The NPU (Neural Processing Unit) Architect will be responsible for designing and optimizing NPU architectures to improve performance, power, area, and flexibility for various neural networks in our series chips. This role will require analyzing existing and emerging neural networks to identify bottlenecks and areas for innovation and applying innovative approaches to design and optimize NPUs. The ideal candidate should have experience in NPU micro-architecture, RTL, simulator, and compiler to refine and assess the feasibility of ideas. Responsibilities Define new NPU architectures and optimize existing ones to improve performance/power/area metric and flexibility for neural networks. Analyze existing and new emerging neural networks to identify bottlenecks and opportunities for innovation. Use innovative approaches to improve NPU architecture. Possess experience in NPU micro-architecture, RTL, simulator, and compiler. Assess feasibility of ideas and refine them. Qualifications 5+ years of experience in hardware design projects in architectural or micro-architectural level. Experience in PPA (power/performance/area) optimizations. Familiar with hardware description languages - SystemVerilog. Programming skills in C/C++. Preferred qualifications Experience in NPU, GPU, and micro-processor development; especially many-core and multi-chip systems. Experience with ML frameworks (Tensorflow, PyTorch, TVM, and so on Experience in architecture exploration tool development. Experience in hardware simulator development. Experience in compiler development. Best Reagrds, Piyush Ranjan Manager, Busniess Development & Service Delivery