Senior Static Timing Analysis (STA) Engineer
San Jose, CA (onsite/hybrid)
US Citizen or US Permanent Resident
6-12 months contract with possible extensions

Required Skills & Experience:
7+ years of experience in Static Timing Analysis
Demonstrate a strong knowledge of all aspects of timing and synthesis for a wide variety of designs
Understand crosstalk, noise, OCV, timing margins
Familiarity with Clock specs, jitter, IR drop, spice analysis
Working with multi-site teams for execution
Work with methodology teams to constantly improve flows and processes
Experience with STA Lead roles a plus
Expertise in developing, implementing, and verifying STA constraints
Expertise in efficient closure of Subsystem as well as SoC-level timing including running optimization on PTECO for timing and Power
Knowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & Route
Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes
Contribute to timing flow and methodology improvements
BSEE required

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Javier Leon
619-227-3193 cell
FJLrecruiter @ (link removed)